OTP Logic Array Physical Design

With the development of computer and communication technology, information security has become more and more important. One-time-programmable logic arrays play an increasingly important role in the way of scientific progress. It has the advantage of higher reliability, strong ability of anti-radiation, and can be widely applied to more complex fields related to the military, aerospace and other highly confidential environment occasions. In this paper, one time programmable logic arrays passed the test, and provide high reference value to future high-performance OTP FPGA design.Through theoretical analysis and testing, based on 0.18μm CMOS manufacturing technique, the laboratory’s self-designed OTP bit unit is applied to the circuit and finally devised a 256 bit logic array. Design work includes bit cell structure design, design of peripheral circuits, the layout design and finally testing. At first, this paper describes the bit cell structure and breakdown theory of the anti-fuse OTP bits. Then introduce working mechanism of OTP cell. Peripheral circuits including programming module, reading test module and function realization module. This paper introduces function of critical circuits in the each module. The two-stage charge pump circuits in the program system control the internal gerneration of high-voltage which will avoid damaging adjacent cells, breaking down wrong chip unit and bad interference to other circuit; two stage latch circuit and sense amplifier works to ensure proper fast reading speed and ensure the stability of data; CLB unit in the logic function unit is to realize logic functions.In the process of layout design, consider the the chip area of layout, the main structure of external circuit and the placement of I / O ports. In the step of designing, also consider the method of global planning and placement, the planning of power, ground signals and the way to route. In addition to considering placement and routing, need to consider the various manufacturing problems: trying to optimize the design, to avoid various bad effects. After physical verification by DRC and LVS by using Calibre, get parasitic extraction from final layout to make sure the basic function of the OTP memory is accurate and the post simulation is proceed. The results of the post simulation are the most proximity data to the result of the actual test of tape-out chip.After tape-out and package, test the chip in two steps through self-built platform. Firstly, test the basic function of programming and reading. Secondly, test the basic logic functions. The test results show that all functions is accurate and achieves the design specifications.