Reseach On Low Power Time Domain Analog To Digital Converter

As traditional high-speed high-precision voltage-domain ADC with advanced CMOS process compatibility problem, the new time-domain ADC architecture of this research achieves 12-bit 100-MSPS based on 55 nm CMOS process domain by exploring the low-gain operational amplifiers to achieve high linearity voltage-to-time converter and borrowing pipelined ideology to breakthrough time-to-digital converter precision limits.Firstly, the basic architecture and performance parameters are introduced. By analyzing the traditional voltage-domain ADC limitations and basing on new ADC architecture trends, the time-domain ADC architecture applied to nanometer process is determined.Secondly, the voltage-to-time converter based on the structure of MDAC is designed and the impact of operational amplifiers and comparators for pulse signal output is discussed. Using the low gain operational amplifier to achieve high linearity, the voltage-to-time converter converts the voltage-domain signal to the time-domain signal to resolve the compatibility problem of analog circuit design with advanced CMOS process.Thirdly, according to the shortcomings of traditional time-to-digital converter, the ability of digital quantization in time-domain is improved by the pipelined ideology. Further,derived the transfer function of time-domain pipelined time-to-digital converter, designed the time registers to achieve real asynchronous quantify in time-domain and optimized pulse-train time amplifier to amplify the time pulse signal with digital correction.Finally, 12-bit 100 MSPS time-domain ADC was designed and simulated based on 55 nm CMOS process. The voltage-to-time converter achieved 2.5 quantization bits and a sign bit in voltage domain, and the remaining 9-bit was quantized in time-domain. The simulation results obtained SFDR of 75.6dB, SNDR of 67.0dB, ENOB of 10.8-bit, FOM of 0.184pJ/conversion-step under 100 MHz sampling frequency.