Research And Fpga Implementation Of Parallel Turbo Encoding And Decoding Algorithms Of Lte-a

As the increasing and improving of bussiness requirement, the broadband requirements of mobile communication system improves. Thus, how to choose a channel coding scheme with good decoding performance and improve the reliability of the transmission appear to be very important. After long-term evaluation, 3GPP chose Turbo as channel coding scheme for the fourth generation mobile communication system——LTE-A. MIIT issued 4G licenses to the three operators in December 4, 2013, which indicate the Turbo will follow much concern later.In the article, I analyzes the suitable algorithm for Turbo encoding and Turbo decoding in LTE-A. For the encoding, we can design according to LTE-A protocol directly; For Turbo decoding, this article firstly studies basic principles for soft demodulation algorithm applicable to LTE-A. And then I analyze and compare the principle, performance and complexity of the four different decoding algorithm(SOVA, MAP, LOG-MAP, MAX-LOG-MAP). At the expense of little decoding performance, I choose MAX-LOG-MAP as the final algorithm for hardware implementation.In addition, the article also analyzes the parallel processing for encoding algorithm and decoding algorithm. The traditional encoding algorithm uses shift registers, whose state at any time prior is related to the input bit concerned, the method can not achieve parallelism in order to achieve high throughput. So I design an implementation method based on lookup tables. Meanwhile, I analyze the QPP interleaver in LTE-A Turbo, which has no address contention and no access violation, Based on it, parallel interleaving and de-interleaving for decoding is studied and simulated. And I analyze the influence of different degrees of parallelism for MAX-LOG-MAP. Since the very effective strategy for initializating sub decoders, parallel MAX-LOG-MAP decoding algorithm loss little performance with respect to the serial MAX-LOG-MAP decoding algorithm(For 8 parallel decoding of 40 bits, the performance loss is only about 0.7dB).On the basis of analysis of algorithms, this article designed a parallel structure for Turbo encoder and Turbo decoder in LTE-A(8 parallelism). And then I analyzes the interface, the core circuit, the simulation result of sub-module, and the total hardware resource consumption. At last, I test the designed circuit in Altera DE4(Chip:EP4S40G5H40I2).Turbo encoder designed in this paper accountes for less than 1% of the overall resources(combinational ALUTs is 477, accountes for less than 1%; dedicated logic registers is 762, accountes for less than 1%), the maximum clock frequency can reach 315.06 MHz, the maximum throughput can reach 2.52 Gbit/s. Turbo decoder accountes for 15% of the overall resources(combinational ALUTs is 47084, accountes for 1%; memory ALUTs is 4826, accountes for 2%; dedicated logic registers is 54251, accountes for 13%), the maximum clock frequency can reach 175.87 MHz, the maximum throughput can reach 175.87 Mbit/s.