Research On None Phase Truncation Error DDS Based On FPGA

In recent years, the requirement for stability of signal frequency and accuracy of electronic equipment which used in radar, communication and other fields becomes increasingly strictly, so direct digital frequency synthesis(DDFS) technology has become research key point and hotspot among scholars. With fast development of modern science technology and manufacturing technology, system structures and the performance of direct frequency synthesis technology have been promoted and optimized in different degrees, but the signal error of this technology cannot be ignored.This dissertation researches the structure of the direct digital synthesis(DDS) technology, focusing on the signal stray generated by DDS, reduces the reason for causing signal stray from aspects of working principle and theoretical derivation, and analyzes none phase truncation error, amplitude quantization error, digital-to-analog converter(DAC) nonlinear conversion error etc of traditional DDS. Then analyzes the difference between common none phase truncation error of DDFS and traditional DDFS and puts a forward a new scheme of none phase truncation error of DDFS which is different from traditional methods. Through Matlab simulation, and combined with FPGA simulation has verified the rationality and feasibility of this design. The main contents include:(1) Introduce and theoretical analyze the structure of traditional DDFS, analyze the main reason for signal stray from the mathematical point and the structure and principle of phase-locked loop(PLL).And then research and analyze eliminate spurious methods, such as dither injection method, ROM compression method and delay overlapping method.(2) Introduce a common method to eliminate the phase truncation error, and put forward a new structure of none phase truncation DDFS, which can reduce the storage depth of ROM without truncating lower phase word case, amend the amplitude which searched by high phase word, and eliminate the error caused by phase truncation. Use Matlab and FPGA to verify the method and functional simulate, compared with the traditional method, this structure can eliminate the phase truncation error effectively.(3) Analyze various schemes of DDFS+PLL, and use the DDFS+PLL program putting the date of the DDFS output signal which without phase truncation error into phase locked loop circuit, such as phase-detector input, frequency divider input, phase-locked loop inside mixer, phase-locked loop external mixer, and use Matlab to simulate no phase truncation error DDFS+PLL method to validate the feasibility of the project.