Algorithm Study And Circuit Realization Of LDPC Based On CMMB

In recent years, mobile terminals update more and more fast. Performance requirement of equipments made by different companies are demanded much more higher. In order to guarantee reliable transmission of information in communication systems, error correction coding is an indispensable part. In practical application, LDPC code is the best performance code of many error correction codes. In the early 21 st century, state administration of radio, film and television put forward the CMMB(China Mobile Multimedia Broadcasting). In order to promote our country’s independent scientific research achievements, CMMB becomes the research hot across the country. As the inner code, LDPC code accomplishes forward error correction in this specification.This thesis not only completes the study of LDPC decoding algorithms, but also completes the decoder circuit implementation and FPGA verification. On these basics, logic synthesis and layout work are finished.This thesis analyses and compares basic decoding algorithms, furthermore, LDPC decoding algorithms with better performance are proposed. One is improved Min2nd-sum algorithm which bases on Min-sum algorithm. This algorithm simplifies Sum-product algorithm and promotes the decoding performance comparing with the Min-sum algorithm which does the same simplify work. The other is the improved layered decoding algorithm. It overcomes unevenness in reliability of the traditional layered decoding. Compared to the traditional layered decoding algorithm with same bit error rate, the performance improves nearly 0.5d B.In hardware implementation process, this thesis analyzes the mapping process of algorithm to hardware implementation, gives full consideration to the balance of area, rate, power consumption and so on. Layered decoding algorithm’s column weight of each column in a layer can’t be more than one during realization process. In order to satisfy the constraint and achieve maximum parallelism, need to transform check matrix equivalently. The posterior probability storage, check information storage and check nodes calculation unit are improved to save areas. First, according to circulation characteristics of the transformed check matrix simplifies posterior information’s read and write operations during the decoding process. Then, compress check information storage. Last, in check nodes calculation unit, the way which is based on pointer and occupies less area is adopted to get the minimum and second minimum values. The multiply coefficient module’s operating order and procedure are changed. It decreases the number of multiply coefficient module and improves operating precision. Partial parallel structure is adopted and ping-pong operation is used in posterior memory to increase speed rate.The test environment is built using VCS platform to fully ensure the correctness of the decoder function, and then hardware tests on Xilinx VIRTEX-5 FPGA is carried out. The throughput rate is 20 Mbps which can meet the 16 Mbps requirement of CMMB standard. Afterwards, logic synthesis and layout work are accomplished to ensure timing convergence.