Structure Optimization And Performance Analysis Of Metal Floating Gate Memory

The flash memory occupies a major share of the market of nonvolatile memories because of its advantages on integration, power consumption, reliability and cost. However, with the development of the microelectronic technology, flash memory is facing serious challenges to meet the performance requirement. The scalability of flash memory based on conventional poly-silicon floating gate will bring in serious reliability issues. To solve these problems, the proposal of replacing poly-Si by metal as floating gate to improve the memory performance is performed and has garnered a lot of attention. This paper concentrates on the metal floating gate memory. In order to enhance the performance, the floating gate was optimized in this study.The electric field distribution of the channel and the potential of the floating gate are the main factors to affect the performance of flash memory. In this paper, the structure of metal floating gate was optimized to study the P/E performance. By optimized the structure of the floating gate, the electric field distribution of the channel was changed, and the electron injection efficiency was increased during programming. During erasing, the increased vertical electric field helped the electrons in the floating gate went back to the substrate by F-N tunneling. The simulation results showed that the programming time was reduced by 77% and the erasing time was reduced by 52% after being optimized for the same threshold voltage shift of 3.5V/-3.5V(in programming and erasing process, respectively), which meaned the P/E speed could be enhanced by optimized the structure of metal floating gate.The SOI technology has a great influence on the performance of the device, so the SOI metal floating gate memory was studied in this paper and a improvement scheme was performed. The simulation results showed that the memory window was improved by 32% and the programming time was reduced by 73% and the erasing time was reduced by 64% for the same threshold voltage shift of 3.5V/-3.5V. The performance of the memory with high-k dielectric was also studied in this paper and the simulation results showed the P/E speed was futher improved.Finally, a new process was proposed to fabricate the proposed structure and the process was compatible with the standard CMOS process. By using simulator Silvaco TCAD, the process flow of the SOI metal floating gate memory was simulated in this paper. The simulation results confirmed the feasibility of the proposed scheme.