The Design, Optimization And Verification Of Fixed-point Multiply Accumulate For X-DSP

Digital signal processor is a speciali embedded microprocessor, which is widely used in modern communication, image processing and radar signal processors.X-DSP is a 64-bits DSP processor by independently developed, which can dissue 11 instructions simultaneously worked at 1GHz. It is implemented with very long instruction word(VLIW) architecture. Based on the X-DSP research and development, this dissertation devises a fixed-point fixed-point mulitply accumulate(IMAC) for 64-bits SIMD, which has the adder, mulitiplication, and moving data functions. The primary work and innovation of this dissertation are as follows:1. The dissertation implements a 32/64 bits sign or unsign SIMD adder with saturation operation and abnormal operation by adopting KS(Kogge-Stone) tree structure of parallel prefix adder. Besides, the mov instruction is devised in addation module.2. Based on Wallace tree multiplier and Booth algorithm, the dissertation implements a 32/64 bits SIMD multiplier which can be used in fixed-point and floating-point mulitiplier with abnormal operation. In this dissertation, the multiplier which is made up of the two 32x32-bit multiplier and two 64x32-bit multiplier is transformed into four 32x32-bit multipliers, The delay of critical path is reduced by 2.2%, the cell area is decreased by 14.5%, power consumption is reduced by 21.4%.3. The dissertation designs the fixed-point mulitply accumulate with reasonable pipeline by analysising X-DSP architecture and the fucitons of multiply accumulate instructions. For fixed-point multiply accumulate, it analyses delay time of the critical path and optimizes the architecture with reasonable methods. Based on 40 nm process, it is synthesized under the typical conditions with the DC tools. The critical path is 450 ps, the cell area is 47672μm2,the power consumption is 35 mw.4. It researches functional points of fixed-Point multiply-accumulate and makes a detailed plan for verification. Besides, it is verified comprehensively with simulations at the module level, system level, and formal verification for fixed-point multiply accumulate.