Design Of LNA For UHF RFID Reader Applications

RFID(Radio Frequency Identification Technology) is a non-contact wireless communication technology with automatic recognition. Widely used in access control system, identity recognition, contactless payment cards, vehicle anti- theft system, logistics system, It has advantage of antimagnetic, high temperature resistant and long read-write distance. Among 4 types of radio frequency identification technology, 860~960MHZ ultra high frequency radio frequency identification system has a promised future for its ability to read multiple tags repeatly and its large data capacity. LNA(Low Noise Amplifier) is the first level of RFID reader. It affects the performance of receiver directly. With the development of RFID in applicants, integrated process and expansion of IC sca le, people expect a better RFID reader with high performance and low power consumption to meet the need of a long battery life in real application scene. In this case, low power circuit design of LNA becomes a research focus.The design of front-end LNA circuit is studied in this paper for the application of ultra high frequency RFID. Aiming at the problem of large power consumption of the LN A circuit, MOS that work in the subthreshold region is used to decrease the current and the transconductance so tha t the system power consumption can be decreased. Meanwhile, the current reuse technique and the optimal noise matching method are used to cover the problem of noise performance and insufficient gain when MOS works in the subthreshold region. Finally, lower power consumption is realized in the premise of good gain, noise performance.Global Foundry 180 nm CMOS process is used in the circuit design, layout design and physical verification of the LNA proposed in this paper. The result of EDA simulation: The LNA we proposed uses 1.8v power supply voltage. Power consumption is 1.8m W. Noise factor NF=3.6d B. The S parameters of the center frequency is S11=-16.5d B, S22=-22.8d B. The system is under good input and output matching. The circuit has a high voltage gain S21=15.6d B with good isolation. The chip layout area is 630×450(without pad).