The Multi-core On-chip Memory Structure Based On EDRAM

Multi-core is the current development trend in microprocessor designing. As the CMOS technology feature size decreases, the number of transistors integrated on unit area gets larger, and the number of cores whithin a single processor increases at the same time. Limited by the area and power, multiprocessors raise a claim for higher performance of the on-chip memory system while scaling to many-core or thousand-core processors. It becomes a key problem for developing many-core or thousand core processors to construct an on-chip memory structure with smaller delay, larger capacity, larger bandwidth.3-Dimensional Integrated Circuits(3D IC) can stack multiple dice on a chip by using Silicon-Through-Vias(TSV), which improves the integrity and decreases the power and on-chip interconnect delay, that expands the design exploration space greatly. The eDRAM technology can integrate the DRAM cells on logic dice using logic-compatible technology. It has a bigger memory density, lower power, smaller delay in big capacity case than the SRAM technology, which can be used to construct the high-speed large-capacity on-chip cache. Combining the 3D IC and eDRAM technology can solve the memory problem faced by multi-core processors while scaling to many-core or thousand core.This thesis introduced general on-chip memory structure model. As CACTI is an outstanding simulator for memory delay, power and area, this thesis studied the characteristics of eDRAM cache using CACTI 6.5, and proposed the Highy Scalabe Memory Model(HSCM2) based on eDRAM. McPAT is a prevailing simulator for multi-core processor power, area and timing. In this thesis, the McPAT is modified to fit actual processors, and then the modified McPAT is used to design the Multi/Many core Scalabe Memory Model(M2SM2), which is expanded to 3D background, and then two 3D M2SM2 structures, 3D M2SM2-A and 3D M2SM2-B, are proposed.This thesis introduces the electrical model of tthrough-silicon- vias(TSV) and proposes a model for the the TSV area, power and delay. This thesis proposes a simple 3D processor model and impoves the McPAT with the model for the 3D processor. At last, this thesis studies the area and power of the two proposed 3D M2SM2 model using 3D McPAT, and points out that, utilizing more advanced technology, using cores with less hardware complexity, combining eDRAM and 3D IC technology, bringing in more levels of cache are the development trends of the future multi-core/many-core processor.