The Physical Design And Optimization Of The X-DSP Vector Proceess Element

X-DSP is a microprocessor of high-bit-wide and high-performance in the 40 nm process, the performance of work is required to achieve 1GHz. As the center of vector operation in the chip, the vector process element has a significant impact on the performance and the area of chip.So it is essential design of the vector process element in the X-DSP design process. Based on the detailed investigation and analysis of the vector process element, we complete the physical implementation of the vector process element meeting requirements on the performance and area by using the appropriate optimization technology of physical design. To complete the physical design of the vector process element, the main task is divided into the following parts:(1) We have a clear impact of the various components on the vector process element by the in-depth investigation of components of the vector process element and the analysis of results of the complier. Saving design area of the vector process element and reducing the pressure on the top X-DSP as the goal to determine the area of floorplan. According to the relationship between the modules, we complete the overall floorplan on the determining area.(2) According the investigation of the hard register files, VMAC module, port and registers, we use the optimization methods of placement to reduce the delay of transmission, reduce the length of path, increase the channels of route. It’s the bias of timing closure of the vector process element.(3) According the affection of the power-network and the clock-network on the vector investigation element, we set the design goals of the power-network and the clock-network combined with the characteristic of the placement and the requirement of the design. In the optimization design of the power-network, we reduce the use of through-hole and divide the routing area of the power-network to achieve the purpose of saving the routing area. In the optimal design of the clock-network, we use the optimized methods of clock skew, clock drive unit, unit driven load, clock-network routing and DCAP physical units to reduce the transmission delay and area of the clock-network.(4) To reduce the impact of interconnect delay and crosstalk on the design performance of design, we have the methods of a connection optimization. We achieve the purpose of optimizing performance mainly through the repeaters and controlling the length of connection to reduce delay of transmission and crosstalk.