Research On PCB-Level Power Distribution Network Modeling

Fast switching of logic circuits and buffers inside the integrated circuits (ICs) results in a fast transient current in the power distribution network (PDN) And the decoupling capacitors used in the power/ground planes provide the charge for switching current, consequently eliminate the transient current. However, the parasitic inductances generated in the PDN impede the current supply to the chip, which results in a significant drop and potential ripples in the supply voltages and leads to power integrity problems for the IC. The voltage drop in the power/ground planes also causes a potential difference in the planes, that able to drive dipole-type antennas, which leads to electromagnetic interference (EMI) problems. The noise in the supply voltage can further couple to the signal traces transitioning through the power/ground planes and cause signal integrity problems. The performance of PDN determines the drop and ripples in the supply voltage. Quantifying the PDN impedance, including the parasitic inductance, is critical for problems associated with power and signal integrity and EMI.There exist different structures of PDN in a complicated electronic system where parasitic inductance could result in power integrity problems in the whole system. It necessitate to model the PDN and provide a pre-layout rules for the design of PDN. Therefore, in this research work, different methods are proposed to model the different structures of PDN.With vias connecting the IC pin, power/ground planes and decoupling capacitors, the inductances of vias between rectangular parallel planes are essential for PDN performance and they are extracted from the impedance based on cavity model. The assumption of uniform impressed current on vias in the cavity model approach leads to inaccuracy when the vias get closer and the diameter of vias becomes larger. An improved resonant cavity model, which considers the non-uniform current distribution resulting from closely spaced vias is presented, that is more suitable for small pitches in the package. A semi-analytical method is proposed to accurately and efficiently calculate the impedance of grid-type PDN on interposer and the semi-analytical method is also useful to predict the electric field distribution of each mode of the grid-type PDN, which is critical for the placement of decoupling capacitors. Finally, PPP is used to model the complicated power/ground planes in multi-layered PCB, including power/ground planes with holes and non-rectangular power/ground planes.