Research Of Typical ESD Protection Design For Integrated Circuits

With the development of semiconductor manufacturing technology, the feature size of ICs (Integrated circuit) is decreasing and ESD (Electrostatic discharge) becomes key element in affecting the reliability of IC products. Different application areas in IC products have different requirements of ESD protection design. By using TCAD(Technology Computer Aided Design) and Barth 4002 TLP testing system, the features of ESD protection devices under the high-voltage BCD process and low-voltage CMOS process are studied. The main contents of this dissertation are as follows:(1) Studying the ESD characteristics of diode and GGNMOS in CMOS process. According to the test data, we analyzed the influences of width and channel length to ESD characteristics.(2) Studying the ESD characteristic of SCR(Silicon Controlled Rectifier) in low-voltage process. The trigger voltage can be decreased through LVTSCR which can be formed by bridging N+ between N-Well and P-Sub. In the 0.18um CMOS process, the holding voltage was too low and we have found that the holding voltage can be increased by elongating the distances between bridge N+ and gate or the channel length.(3) Based on the large array LDMOS in 0.35um BCD process, the ESD characteristics have been studied. The LDMOS has 2KV ESD self-protection ability of HBM model when its width exceeds 15000um. Increasing the distance between drain contacts and gate can make failure current bigger, but it will result driver ability getting worse.(4) The degradation phenomenon of LDMOS trigger voltage under repeated TLP zaps have been studied. This phenomenon was caused by the filament in drain N+ which can be inferred from test data and TCAD simulations. By inserting P+ between drain N+ and gate, trigger voltage degradation can be avoided.(5) The degradation phenomenon of ESD characteristics in LDMOS and LDMOS-SCR when under high ambient temperature is studied. The leakage current of both devices can increase sharply to milliampere level and the trigger voltage and robust ability of LDMOS-SCR will decrease.(6) Studying the development history of TVS and presenting a multi-channel TVS array which is based on diode-trigger LVTSCR. The ESD characteristics were compared between single diode-trigger LVTSCR and packaged TVS array.