Design Of A High-precision Δ-∑ Modulator For Audio Codec

Nowadays, the increasing performance of the Mobile consumer electronics has thrown a thirst on high precision audio signals where analog-to-digital converters play important roles. Aiming to meet the acquirement on the applications, this thesis proposed an audio Δ-∑ modulator featuring with high precision, low power consumption and high dynamic range.The thesis chooses an audio delta-sigma topology concluding switched operational amplifiers, and set the main research aim at the Δ-∑ modulator. At first, the coefficients can be calculated through Matlab/Simulink, taking the non-ideal characters like thermal noise, flick noise and DC offset into account. Next, the algorithms for data weighted average are calculated and compared, simplifying the algorithm and reducing the power and area to the most. In circuit design, the switched capacitor integrators whose op-amps are powered on during half of the period are introduced into the system to save power. Chopper structure is for suppression of flick noise. As for Quantizer, two types located in the circuit make a comparison of the power consumption and area. Combining all the parts above, a high precision, low power, high efficiency A-2 modulator system is fulfilled.Circuits and layouts based on the GlobalFoundries 0.18μm BCD 1P4M process occupying nearly 1012μm×995μm. Simulated results reflect the SNDR of 110.6 dB. The input signals are -4.35 dB. Power consumption is 4.95 mW and the FOM is 428.18 fJ/Conversion-step. Performance degradation does not occur in post simulation. The chip is already taped out.