Research And Design Of Analog IP For System Chip Based On 65 Nm CMOS Technology

Along with the rapid development of the design ability and technology, which make it possible to design a system on chip (SOC). SOC has greatly improved the performance of the product since it came out. With the improvement of the integration and complexity, the technology of IP (Intellectual Property) reuse become particularly important, which successfully resolves the contradiction between integration scale and design efficiency. While analog IP as an important part has a direct impact on the performance of the SOC, the demand for analog IP’s accuracy, power consumption and area is quite strict. With the development of technology, the analog devices are more susceptible to parasitic effects and process variations. As a result, the existed analog IP can’t meet the demand of high accuracy. This paper will study and design an analog IP particular for secure SOC, which are based on nano technology.Firstly, this paper introduces the IP’s development backgroud and current situation of the research, and makes a summary of the different IP design methods.Then this paper studies on the key circuits which are commonly used in analog IP, such as bandgap circuit and comparator, and this paper has made an analysis of the circuits’basic theory and common structure. According to the specification, based on SMIC 65 nm CMOS process, this paper implements a voltage detector IP and a frequency detector IP with high accuracy.This paper presents a voltage detector IP based on a low supply voltage bandgap, which can be used to accurately detect the voltage ranged from 0.9 V to 3.3 V, and the voltage threshold can be customized set. In this paper, the circuit of module has been analyzed in detail, and the layout design has been finished, with an area of 0.37 X 0.31 mm2. The simulation results show that the detection error can be kept within 1% from -40 to 100℃, and the power consumption is 25μW.Then the paper presents a frequency detector IP based on traditional frequecy detectors. The frequency detector IP is designed with the combination of the digital circuits to control and analog circuits to detect. It achieves multi frequency detection with high detection accuracy, low power consumption and small size. And the multi gear frequency threshold can also be set through programming by users. The final layout is presented in the paper with an area of 0.19 X 0.11 mm2. The simulation result shows that the detection variation is can be kept within 1% from -40 to 100℃, and the power consumption is ±2%, while the total power consumption is 67.3μW. The all results can meet the demand.The two analog IP mentioned above have been applied in a security SOC, and they are now tape out.