| Parallel communication between chips requires enough pins to cover all the data bits, because each data bit in one chip connects to the corresponding bit in the other chip directly. However, the size of pins in packages can not decrease as the size of transistors in chips. So it certainly limits the speed of chip integration and increases cost. At the same time, the requirement of the clock synchronization of parallel communication is relatively higher, so it limits the increment of the speed of transmission interface data rate. All of those suggest that the speed of traditional parallel data transmission has become a bottleneck of data transmission. As an asynchronous mode serial communication, SerDes gradually becomes the mainstream in communication system which requires less pins and can achieve a higher data rate.This article describes a PLL (Phase Locked Loop) which provides clocks for SerDes system based on IEEE 10GBASE-KR protocol. As a very important module of the clock generator, PLL is also the main source of random noise. Its jitter performance affects BER (Bit Error Rate) performance of the system. Under the 10 Gb/s high communication data rate, realizing low jitter clock which satisfys the requirement of system bit error rate becomes the challenge of this design.Based on SMIC 40 nm process, a 5GHz PLL has been designed for 10 Gbps high speed interface circuits in this article. Through the analysis of loop transfer characteristics, relatively optimized specifications have been set. To keep the PLL have a better jitter performance, the frequency of reference signal of PLL has been chosen as classic 156.25MHz. The loop bandwidth has been chosen as 3MHz to suppress phase noise of QVCO further. Series quadrature voltage-controlled oscillator (S-QVCO) has been employed to generate 4-phases 5.15625GHz clocks in the PLL, which has better phase noise performance. Followed /2 divider and single-to-differential buffers are used to generate 8-phases 2.578125GHz clocks with negligible phase error. A technique of Multi-phase rather than only improving the operating frequency of PLL is used which can achieve a higher output frequency. Cascade current mirror structure is used in CP (Charge Pump), and negative feedback technique has been used in charge pump to improve up/down current mismatch as well.In this work, a PLL has been designed which can achieve 5.15625GHz clock and 2.578125GHz clock parallel output phases simultaneously under SMIC 40nm process. It consumes 7.6 mA under the supply voltage of 1.1 Volts. The simulation results show that, the FoM of VCO is about-183.97dBc/Hz at 3MHz offset frequency which is a relative better performance. Through the analysis of each noise contributor, the jitter of the output of 5.15625GHz frequency is about 107fs (rms) in 10 kHz to 100MHz frequency range which meets the lps(rms) system requirement. The lock time is about 1.5us. And the total die area of the PLL is about 780um*410um. And it meets the requirements of the system index. On the other hand, the influence of transistor leakage current under advanced technology on the loop has been analyzed. The current compensation is adopted to compensate this influence, and its output spur performance improves about 2.17dB. |
