Design Of LTE Downlink Physical Layer Interference Scheme In Hybrid Real-Time Test Platform

Along with the development of communication technology, it’s more and more close to the practical application of the scene to be evaluated for algorithm simulation and test verification. The traditional algorithm could be verified for a long time in the pure software simulation platform which couldn’t simulate real link scene and the limited data length was received for a long processing time. If the actual scene needs to be considered in real time test verification, the traditional test can’t be supported. The project of system level multi cell multi terminal technology verification platform was combined and the thesis took Universal Software Radio Peripheral-Reconfigurable I/O (USRP-RIO) and reflective memory card as the hardware platform to realize the Long Term Evolution (LTE) downlink physical layer interference users’ design in hybrid accelerating platform. The design of hybrid real-time test platform was completed and the interference users was added in the thesis. The following three parts were included in this thesis.In the first part, the LTE physical layer and the key technology of software and hardware were introduced. Real-time system which based on LTE protocol architecture was designed, the LTE downlink physical layer system structure and LTE frame structure were analyzed. Medium Access Control (MAC) layer and physical layer were included in the LTE protocol architecture which worked software and hardware platform.In the second part, the mixed real-time platform module was studied, which included Transmission Control Protocol/Internet Protocol (TCP/IP), reflective memory technology, User Datagram Protocol (UDP). The actual multi-cell multi-user scheduling scenarios and the hardware the software and hardware were increased in the loop test program and software of the test equipment were verified in the loop performance, which simulated the interaction process between the MAC layer and the physical layer in the real link scenario. The generic processor with Field-Programmable Gate Array (FPGA) heterogeneous platforms were connected by the type of reflective memory. The performance of the test platform was verified, and the throughput and delay of the data could meet the requirements of the industrial level.In the third part, the user’s design module was designed, which included the generation of interference data and the addition of the data in the physical layer. Firstly, based on the underlying framework that LTE physical layer algorithm was implemented by the hardware of USRP-RIO, according to the scheduling interference level power information of Resource Block (RB) which was transferred by real-time hardware platform from the MAC layer, six RB level interfering users for intercell were added to the target user in the receiver of physical layer. Secondly, according to the power offset information which was transferred by the combination of hardware and software of real-time platform, nine interfering users were relative to target user were added at the send end of physical layer and modulation mapping process were designed. Finally, the interference was added successfully and transmit power spectrum, Physical Downlink Shared Channel (PDSCH) constellation, throughput, Signal to Interference plus Noise Ratio (SINR) and Block Error Rate (BLER)were analysed.