Research And Design Of Ultra-low Power Consumption Phase Locked Loop

As the integrated circuits technology node is lower and lower, the ultra-low power consumption becomes an important challenge to the IC design. IEEE802.11 protocol is the important standard of wireless local area networks communication which uses 2.4GHz frequency ISM band widely in order to improve the ability charge of battery life. What’s more, the critical factors of SOC and NOC systems are determined by the ultra-low power consumption. The use of portable Wi Fi instrument has already fairly common, PLL(Phase Locked Loop) which can produce the high speed clock on the chip, is an important part of the transceiver. Also consumption of PLL has an obvious effect on the whole transceiver.The demand of the chip design changes from the simple pursuit of high performance and small area to the comprehensive requirements for power consumption. The increasing chip operating frequency, more interconnected parasitic resistance and capacitance promote the increase in power consumption. What’s more, the scale down technique results in the leakage current which is becoming more and more serious. All of these bring the challenge to the design of low power phase-locked loop.This thesis based on the research of ultra-low power consumption’s design technology, duing to the loop analysis and consumption research of PLL, designs a ultra-low power PLL with SMIC 0.13μm IP6 M CMOS process by mending the module which consumes large power. The main content is as follows.1) Do the analysis of the IC consumption. To get the main factor which influences the power consumption by doing a research of the static power consumption, dynamic power consumption and short circuit power consumption. What’s more, it researches of the power consumption’s tendency under the situation of deep submicron processes. Based on the condition, it introduces a low power design technology which is used in common.2) Do the analysis of the loop of PLL. It establishes the loop parameter by doing mathematical modeling of every module; optimizes the loop with the help of the Verilog-A language continuously. By means of researching of PLL’s consumption and analysing the power consumption of the LC oscillator, it points out the rules of the lower consumption design. After the reduction of process node makes the leakage current become an important factor which influences the PLL’s performance, it makes the conclusion about the leakage current of PLL and then provides the measures to restrain the leakage current.3) Design the important modules such as VCO and Divider. It adopts the current reused technology to half VCO’s tail current. Aimed at improving the structure of the TSPC to reduce the amount of transistor accumulating on branches, it takes advantage of METSPC’s trigger design frequency divider which not only depresses their branches’ capacitance but also is suitable to low power supply voltage applications.4) Do the layout design to PLL and give the result of post simulation. It displays low power characteristics of the design in comparison. The simulation results show that it designed a low power PLL in this thesis. And its output frequency is 2.4GHz, and the deterministic peak-peak jitter is 4.29 ps, the RMS jitter is 0.105 ps, and the power is 3.8642 m W.