The Key Technology Of High Speed Image Data Real-time Storage And Display

In the aerospace test, high frequency frames, high resolution images sensors are widely applied to obtain high clear and high resolution image. The use of these high-performance imaging devices will generate a large amount of image data in a short period of time, which is a great challenge for storage test systems. In order to realize large capacity, high storage speed, low power consumption, high flexibility and high reliability storage requirements for image data, this paper is dedicated to the study of a kind of high-speed real-time image data storage and display device, especially the three key techniques.First of all, a universal high speed and large capacity data storage scheme is proposed. The high capacity Flash NAND chip is used to form a memory array, which can achieve sustainable high speed storage of the input image data through the pipeline operation and bit expansion operation. The dual pipelining parallel working mode based on two-level caching mechanism is realized in FPGA, Which make a full use of each storage performance of NAND Flash chip to realize the sustained and rapid storage a large amount of data. And according to the characteristics of the Flash storage array, two kinds of invalid management solution are proposed, which got its own merit. The ECC error correction algorithm which is recommended by the chip manufacturer is adopted to correct the error code in the Flash chip, realizing reliable storage of the data under the high throughput.Secondly, querying to achieve the maximum value and the minimum value of a frame image data using the large capacity block RAM resource within the FPGA. After that call the IP core to complete the multiplication and division operations, and finally realizes the conversion of 16-bit gray image to 8-bit to adapt to the requirements of VGA display. Furthermore the FPGA was used to construct the VGA display timing, and through the control of the ADV7123, real-time display of the input image data is achieved.Finally, aiming at the time series stability problem caused by the internal complex logic sequence of FPGA, the method of using FPGA internal storage resources to build a high stability and low power consumption finite state machine is studied. This design method greatly reduces the use of logic resources and wiring resources within the FPGA, so as to achieve the goal of reducing power consumption and improving the reliability of the system.By analyzing and calculating the test data based on the technologies as well as overall performance test device, the high-speed image recorder using 20 Flash chips implementation of 5 x 8 storage array can achieve the continuous data storage rate of 200 MB/s to the max. A large number of tests show that the storage speed, capacity and the display effect of the high-speed image recorder are all satisfied with the design index, and the work is stable and reliable.