Hot-Carrier Effect Study At Room Temperature On 0.18μm Partially Depleted SOI H-Gate NMOSFET

Silicon On Insulator CMOS technology is attractive in aerospace, military application since they provide full dielectric isolation and reduced junction capacitance as compared to bulk silicon devices since the last centry.During the long term operation of their lifetime, reliability issues such as hot carrier injection (HCI), negative bias temperature instability (NBTI) should be considered. They could degradate the performance of circuit and reduce circuit lifetime. Thus, the reliability mechanism became an importance research topinc in military research center.Partially depleted SOI (PD-SOI) devices’s threshold voltage have threaten from the back gate decoupling effect and floating-body effect, TID effect. To avoid these effects, new structures have been developed as body contact configuration, H-type structure which made the hot carrier injection effect more difficult.In this work, we study a 0.18μm PD-SOI H type gate NMOSFET. Electrical stress has been applied on the NMOS to study Vth, Gm, and Idsat degradation for different size devices. The work has four main points:1) Improve the HCI test set-up and measurement flow for SOI device;2) From basic physical model to extract device parameter degradation fomular(the relationship beween device parameter and stress conditions)3) Add a HCI degradation model into PD SOI NMOSFET SPICE model, and applied on a ring oscillator test circuit to do the verificationFrom the research, SOI based device parameter degradation has a power law relationship with Vds and Vgs, has a exponential relationship with channel length. The channel width do not impact HCI degradation. We build a TCAD simulation for NMOSFET and simulate channel electrical field to show the electrical stress dependence.