Research On Double Gate MOSFET Incorporating Dielectric Pocket(DP)

In recent years, with the rapid development of electronic industry, the requirements of chip integration and performance of miniaturization MOS device become more and more higher. After the device size goes into nanometer level, various kinds of negative phenomena appear which will affect the performance of device directly or indirectly. In order to alleviate the impact of these problems on the device, the solutions can be list as follows:First, to find new device structures and new material preparation process; Second, to use new manufacturing process technology; Last, to find the theoretical model which can bring better performance. This paper use the first solution to study a new structure called DPDG (Dielectric Pocket Double Gate) MOSFET. It bases on the structure of double gate MOSFET, which add a DP at the edge of source and drain region. With DP structure,the shared charge between source、drain and channel becomes weaken,breakdown characteristics and the control capability of the gate are improved and short-channel effects (SCE) is suppressed. Therefore, it is more suitable for high temperature environment and the reliability of the device is improved. DPDG MOSFET becomes more and more popular in small devices and it has became one of the best candidates in the nanometer CMOS circuits design with high-temperature.Based on the DPDG MOSFET device structure, electrical characteristics in channel are simulated through the simulation software Atlas in this paper. Body potential and the electric field of DPDG MOSFET and DG MOSFET are also simulated. It is found that the potential and electric field at the surface of the insulating column in the source-drain channel reduce greatly. Thus, DPDG MOSFET has more advantages to suppress Hot Carrier Effects (HCE) and SCE. The carrier mobility in the channel center, Id～Vds characteristics and Id～Vgs characteristics are also simulated. Finally, sub-threshold voltage (Vt), sub-threshold slope (SS), drain induced barrier lowering (DIBL) at different channel length are analyzed. The results show that the influence of HCE and SCE on the device can be reduced and the the reliability can be improved.In this paper, the two dimensional Poisson equation is established by using the channel between the source and the drain dielectric pocket in the Cartesian coordinate system. Using the parabolic approximation method to solve the equation, the drain potential model on the surface of the dielectric pocket is obtained. Using the simulation tool atlas, modeling and simulation results under in the linear and saturation region with different drain voltage is analyzed and compared. Also,the results under the different gate length are also compared. The accuracy of the model is analyzed and verified.The influence of temperature on the performance of DPDG MOSFET is discussed and analyzed. Through the Atlas simulation software, we simulate Id-Vds curve, Id-Vgs curve, mobility, and SCE distribution of devices under different temperature environment. It was found that the temperature has great influence on the performance of the device, since the temperature is more higher, the device performance is more worse. In high temperature environments, performance of DPDG MOSFET is better than DG MOSFET. Finally, the performance optimization of DPDG MOSFET is analyzed from the properties and structure of insulation column. It can be seen:higher height of DP or use a higher dielectric constant oxide as material can improve the performance of the device effectively; the structure with DP both in source and drain has more advantages in inhibiting SCE that compare with the DP structure only in drain.These improvements allow the device in high temperature environments easier to maintain its performance.