Research Of 12-bit High Speed Low Power Consumption Pipeline ADC Based On Equalization Algorithm

As the demand of high speed and high precision analog to digital converter in various fields of modern society becomes more and more urgent, designing a high precision and high speed ADC is more and more important. Because domestic technology foundation platform is not perfect and the accumulation of circuit design ability is less. there are a lot of difficulties in the product realization in the design of high speed and high precision analog to digital converter, leading to the domestic ADC product of the high speed and the high precision is still in a blank almost. A 12 bit 1GS/s low-power dissipation pipeline ADC is designed and verified basing on equalization calibration algorithm in this paper.First of all, the equalization calibration algorithm model is established in this paper, analysis of the calibration principle and the realization way of equalization algorithm. And the model of some non-ideal factors in equalization algorithm is established and analysized. Thereby determining the block structure of 12 bit Pipeline ADC basing on the equalization algorithm is 2.5 + 2.5 + 2.5 + 6 structure. Fisrt three stage is 2.5 bits MDAC, and final stage is FLASH ADC of 6 bits.Then, under the determining architecture of Pipeline ADC, the indexes of each main Pipeline ADC circuit module is modeled analysized and determined. And main circuit module is designed and simulated. After the research and analysis of 12 bit 1GS/s low-power dissipation pipeline ADC basing on equalization algorithm, sample and hold circuit is adopted in this paper. Sample and hold circuit adopt closed-loop operational amplifier. It is the same to MDAC. And the design and implementation of gate voltage bootstrap switch increased in the MDAC. All of those help improve the linearity of equalization calibration algorithm. Also some auxiliary function module of a 12 bit pipeline ADC basing on equalization calibration algorithm is compiled using verilog code.Because various non-ideal factors in the actual MDAC will make the output of the op-amp have fixed difference disorders. And there are different k values and constant terms in MDAC because of the different piecewise interval. The equalization correction algorithm used in practical circuit of pipeline ADC is verified and improved. Corresponding to this, equalization algorithm will have corresponding change, and become a little more complicated than the original ideal code validation algorithm. but the core of the main principle and the algorithm does not change too much. MATLAB code completes the digital circuit simulation of the equalization algorithm, verify the research of the 12 bit 1 GS/s actual pipeline ADC basing on the equalization algorithm.Basing on the 40 nm CMOS, verification results of equalization correction algorithm of the pipelline ADC actual circuit show that the equalization algorithm can realize design of a 12 bits 1 GS/s low-power pipeline ADC in single channel. Under the high sampling frequency of 1 GS/s, the frequency of the input signal is 165.7 MHz, spurious free dynamic range(SFDR) of Pipeline ADC is 78.4 dB, signal to noise distortion ratio(SNDR) of 64.9 dB, effective number of bits is 10.5. The power supply voltage is 2.5V, and power dissipation is 350 mw.