| Low-Density Parity-Check Code(LDPC) is a kind of linear group codes with near Shannon Limit. Be-cause of the perfect performance in coding, the low complexity in decoding and the high parallelism in decod-ing, LDPC has been chosen by many communication standards. Referring to the implementation of LDPC decoders, the architectures of ASIC, DSP and so on are facing many questions. For example, the structure is fixed, the throughput rate is low and the code rate is usually very limited. All these questions lead to the requirement of new architecture for decoder. As the communication standards are various and develop in-dividually, the traditional Hardware Defined Radio(HDR) is changing to Software Defined Radio(SDR). Coarse-Grained Reconfigurable Architecture(CGRA) is known for its high flexibility and near ASIC perfor-mance, which meets the demand of SDR.This thesis proposes one CGRA decoder, RaSP-D(Reconfigurable Signal Processor for Decoder), ac-cording to the features of LDPC decoding algorithm, Normalized Min-Sum Algorithm, and characteristics of its Data Flow Graphs. The design is aiming at the high throughput rate, the low bit error rate and the high flexibility. The main research points are shown as followed. (1)The comparison between complexity and performance of different algorithms in decoding QC-LDPC codes is conducted. The Normalized Min-Sum algorithms is chosen. (2)The structure of reconfigurable computing arrays is proposed based on the analysis of the processing elements, the routing structure and the access interface of the arrays. In order to rise the utilization rate of the arrays, the multi-functioned processing elements, the fusion-step routing structure and the various access interface are conducted. (3)The structure of the memory is designed with the low-conflict task division mechanism, the multi-level storage structure and the self-adapted access mode, which improve the performance of memory. (4)The whole working routine is defined in detail and the mapping of algo-rithm’s kernel steps is conducted on RaSP-D. According to the example of mapping in this thesis, the average utilization rate of computing arrays in RaSP-D is over 75%.The experimental results show that the proposed RaSP-D architecture is adaptive to many decoding environments. The peak throughput rate is over 1 Gbps and 1.54 Gbps in rate 5/6. Comparing to the state-to-the-art architectures,such as ASIC and DSP, RaSP-D not only meets the requirement of LTE-A, but also achieve higher flexibility. The RaSP-D can satisfy the coding demand of LTE-A and shows superiority of flexibility in computing and adaptation in algorithms. |
