Design Of A Fast Search Algorithm For H.264 Integer Motion Estimation Module

Integer Motion Estimation (IME) is a key component of H.264/AVC encoder and its design has greatly led to the performance of inter-frame encoding. However, the computation burden and the lengthy process makes IME become the bottleneck of real-time video encoder. In conventional architecture of hardware, it is hard to adopt suitable fast search algorithm to reduce the amount of computation. Therefore, this thesis presents a Down-sample Local Full Search algorithm with an efficient hardware design.Based on a four-stage pipelined architecture of H.264 encoder IP, the DLFS algorithm and its hardware implementation are designed for IME in this thesis. On the base of analysis and assessment of IME full search algorithm and some other classic fast searching algorithms, the method includes a two-stage fast integer motion estimation algorithm and the snake search and calculation are performed in different search ranges. First of all, in the coarse stage, down sampling on the search points is performed along both the horizontal and vertical directions starting from the center of the search range. Besides, only the 16×16 MB partition size is processed to select 3 best candidates in this stage. Then the fine stage expands a new search window around the selected candidates obtained by stage 1 and performs the local full-search blockmatching operations on the search points to determine the best motion vectors for all the 41 blocks of 7 modes in IME. In hardware implementation,256 PEs are used to keep a certain degree speed of calculation and the coarse stage and fine stage share the same calculation module to reduce the consumption of the hardware. Finally, when the hardware design is done, the functional verification of both module-level and system-level is completed under the SoC simulation test bench.The PSNR loss of the DLFS algorithm is less than 0.15dB, with the test of five standard sequences of different resolutions. The IME process of a single MB can be done within 467 cycles. The IME module can meet the requirement of encoding high-definition 720P 30 frames per second at 50MHz, with 98.7k gate count under SMIC180nm process.