Low Power Design And Aging Resistance Technique For Integrated Circuit Using A Linear Programming Approach

As technology scales, the performance and density of VLSI circuits are increasing dramtically; as a consequence, the reliability issues have become main concerns in VLSI design. Among these reliability issues, N BTI induced delay degradation and excessive power dissipation caused by leakage c urrent are two primary failure mechanisms for CMOS devices. In order to solve these problems, two input vector control(IVC) methods based on integer linear programming(ILP) approach are presented to reduce the delay degradation and power dissipation. The proposed methods can increase the reliability and extend the service life for VLSI circuits.In this paper, the modeling methods for N BTI effect and leakage power are presented firstly. Then, the impact of input vector on delay degradation and leakage power are analyzed. Based on this, two IVC methods are proposed to reduce the delay degradation and power consumption of the circuit which focuse on different design requirements.In the case of the sufficient timing margin, this paper mainly focuses on the optimization for the leakage power dissipation. An adaptive leakage power reduction strategy based on a linear programming approach is presented. Firstly, the impact of NBTI- induced transistor threshold voltage change on leakage power of the circuit, as well as the MLV selection, is analyzed. Then, the closed- form relationship between the leakage power of the logic gate and the threshold voltage degradation of internal transistor is generated using support vector regression. After that, the total lifetime of the circuit is divided into a succession of time intervals, and the MLV used in each interval is updated according to the internal transistor’s threshold voltage degradation so that the best overall power reduction result can be achieved. In constrast, in the case of strict timing requirements, the delay degradation and leakage power should be optimized simultaneously. In this paper, we first analyze the different impact of input vector on the degradation and leakage. Based on this, a novel N BTI and leakage reduction criterion function, as well as the corresponding ILP formulation, are presented to simultaneously minimize the delay degradation and leakage power.In order to verify the effectiveness of the two proposed methods, simulation experiments on multiple selected ISCAS’85 and ISCAS’89 benchmark circuits are imp lemented. The experimental results show that compared with the traditional IVC methods, the two proposed methods can further reduce the delay degradation and leakage power, which can meet different design requirements for VLSI circuit. The proposed methods can be applied to the VLSI circuit design, such as the So C, FPGA, et al., which can improve the service life and reliability of the circuit.