| Due to making use of atomic clocks with very high accuracy in satellite and being supported by ground maintenance system,satellite broadcast system timing is widely used in communication systems,electrical systems,military filed and other fields which require high precision timing information.This thesis will physically implement the Verilog code of a low-power GPS timing algorithm to design a GPS timing chip,as well as fabricate and test this chip.The physical design of the chip is from the Verilog code to tapeout.Firstly,the RTL code is synthesized according to the DFT flow,which is followed by the static timing analysis(Pre-STA);and the comparison between the RTL code and the synthesized netlist is performed by formal verification;by making use of ATPG toolkit,a test pattern is generated and the test coverage is analyzed according to the test protocol file;the synthesized netlist is automatically placed and routed based on the digital IC backend design flow;the Post-STA is performed after parasitic parameter extraction of the layout,then followed by the second formal verification between the original RTL code and the netlist extracted from the layout;finally,the final GDSII file is exported to tapeout after DRC and LVS check.Except the digital module,two additional analog modules are integrated on chip,a voltage regulator(VREG)and a 1024x3 8bits dual-port random access memory(DPRAM),the VREG generates 1.8V for the core power supply and the DPRAM is used to support the high-speed acquisition and tracking algorithm of this work.Clock gating is used in the circuit,cut off the clock of the acquisition and tracking blocks to increase the power efficiency when the chip completed timing.This thesis does the physical design for the GPS timing chip from RTL to layout with SMIC 0.18um CMOS technology.The die size is 2.16x2.16mm~2.This chip taped out and tested successfully.The chip works with the low power consumption,low cost and small volume,and it can be widely used in daily life,and will have a very substantial civil market. |