Design Of Digital Buck DC-DC Converter Based On State Feedback Algorithm

With the development of microelectronics technology, the function integrated in electronic equipment and the users' requirement of the performance of the power supply increases. DC-DC converter is widely used because of its high efficiency, small volume and light weight. Compared to analog control, digital control DC-DC converter becomes the development direction of switching power supply for its programmable ability, short design cycle and high reliability.The steady state and transient performance of digital Buck DC-DC converter is closely related to the control algorithm. This paper provides a state feedback control algorithm containing integral element based on particle swarm optimization algorithm. The given control algorithm which adopts pole assignment method, establishes a direct and clear function relationship between poles of transfer function and overshoot, rise time, and adjust time of the unit step response of digital Buck DC-DC converter reference voltage to output transfer function. As long as expected poles are chosen according to the expected unit step response, and then moves the current poles to the expected pole position by state feedback control, the desired unit step response can be obtained. Compared with the conventional frequency domain method and empirical method, the provided algorithm is simpler, more direct and accurate. For eliminating steady-state error of the unit step response of the pure state feedback control digital Buck DC-DC converter, the integral element is added to the pure state feedback control. Aiming at the problem that artificial selection of poles based on experience is hard to guarantee the performance of digital Buck DC-DC converter optimal, particle swarm optimization algorithm is adopted to search optimal poles within the scope of the expected poles, while using function J which contains overshoot, rise time and adjust time as objective function, so as to ensure the comprehensive performance of the digital Buck DC-DC converter optimal.FPGA experiment results on the digital Buck DC-DC converter, whose typical value of the input voltage, output voltage and rated load current are 5V,1.8V and 1A respectively, based on the given state feedback control algorithm show steady-state error of about 1.11%, output voltage ripple of about±1.3%, no overshoot and settling time of about 8ms during startup stage, recovery time of less than 0.49?s/mA and overshoot of less than 0.275V/A when load current step changing, line regulation rate of 2%, load regulation rate of 1.54%, which means the given digital Buck DC-DC converter has good steady state and transient performance.