Research On Phase-Locked Techniques Under Unbalanced Power Networks

The synchronous rotating reference frame phase-locked loop(SRF-PLL) is an effective grid synchronization technique due to its excellent accuracy and dynamic characteristics under ideal grid condition, which has been widely applied in the power electronic converter systems. However, in order to filter out the influence of harmonic disturbances under non-ideal grid conditions, SRF-PLL needs to reduce system bandwidth or join filters, which will reduce dynamic response speed of PLL system. But system bandwidth will be significantly reduced in the presence of low frequency harmonic or negative sequence component, then, dynamic response is difficult to be improved. Therefore, it's necessary to compromise steady- state performance and dynamic performance.In order to accurately analyze the performance of PLL system, this paper firstly establishs SRF-PLL linearized mathematical model based on the basic principle of phase-locked loop, and gives the PLL system design procedure from the aspects of system stability margin, dynamic performance and disturbance rejection capability, which can be used to design general PLL system.To research PLL performance under three-phase unbalanced grid, this paper respectively chooses a multipe reference frame based PLL(MRF-PLL) based on the filter of dq components, a dual second-order generalized integrator based PLL(DSOGI-PLL) based on the filter of ?? components and a two-modules complex-coefficient-filter-based PLL(TMCCF-PLL), and analyzes the impact of each parameter on system performance. Combined with complex coefficient filter theory, this paper analyzes the relationship between different forms of filters, and derives the conclusion that three PLL methods can be equivalent to a second order complex coefficient filter. The experimental results have verified the accuracy of theoretical analysis by constructing hardware platform based on DSP controller.To accelerate the dynamic response speed of the PLL, this paper adds a parameter degree of freedom based on second order complex coefficient filter, which effectively improves its dynamic performance through parameters optimization. Moreover, on the basis of the principle of delayed signal cancellation(DSC), this paper discusses how the cascaded DSC based PLL(CDSC-PLL) to design in the dq coordinate frame and to apply in the ?? stationary coordinate frame. To pursuit faster dynamic response speed, this paper improves the controller of CDSC-PLL, and proposes a parameters optimization process, which can achieve fast dynamic response speed under abrupt input and good harmonic suppression. Finally, the correctness of the proposed method and effectiveness of design are verified by the simulation and experimental results.