Research On Design And Test Technology Of Kalman Filtering Hardware Acceleration Module In Guidance SOC

Precision guidance is vital to weapons in the modern warfare,where the excellent instantaneity and miniaturization of the guidance system are highly demanded considering the increasingly complicated environment.Due to the highly increasing integration level of the circuit,the traditional way by accelerating the clock speed to improve the performance of the microprocessor has approached its bottleneck.It is quite a promising alternative to use hardware acceleration technology module as a co-processor to handle the complex number computation.Embedding the module in guidance SOC as Intellectual Property(IP)core also caters well for the requirement of miniaturization.The thesis is mainly focused on the research of design and test technology of Kalman filtering hardware acceleration module in guidance SOC,and two aspects are involved.Considering the real-time requirement,the basic type of matrix computation in Kalman filter,matrix multiplication,decomposition and triangular inversion,are processed with resource-saving designs of hardware acceleration architectures respectively.Based on the systolic array,acceleration architecture is designed for matrix multiplication.Combined with block matrix multiplication algorithm,the design can be expanded easily and play a role in high dimension matrix multiplication.According to the principle of matrix decomposition,the “processing element(PE)” is designed.A “pipeline technology” is introduced to get the system run at a higher clock frequency,and a “time-sharing technology” is used to improve the computation efficiency via PE-reusing.The data-flow is controlled with the guidance of a self-designed counter,called “Scheduling Counter”.In the process of triangular matrix inversion,on the basis of the possible data dependence analysis,the computation is parallelized with data-flow scheduling mode.A Kalman filter hardware acceleration scheme is proposed,and the qualitative analysis of which shows that our design balanced well among the resource consumption,the ability to fit the needs of various models,and the computational accuracy.Research is developed on the topic of Kalman filter IP core and its test technology design.A design thought is carried out with an emphasizing on its configurable parameter.Considering the test wrapper design and test segregation,a test scheme of Kalman filter hardware acceleration IP core is proposed.