Design Of A CMOS Silicon Cochlear Filter With Ultra-low Power Consumption

At present,it is an international mainstream by using cochlear implants to help the deaf patient restore hearing,it can accurately transform the sound signal from outside world to corresponding electrical signals and then stimulate the residual auditory nerve of the patient to enable their brain to perceive the sound.Recent years we have seen many progressive studies on the implementation of silicon cochlea in analog VLSI which are mostly driven by the increasing demand for high performance and power efficient auditory processing chips in biomedical applications as well as portable consumers.An essential building block of a silicon cochlea is the filters,as input signal needs to be separated into multiple frequency channels.Besides,the frequency response of the filters must be highly adjustable so as to achieve the active gain adaption and sharp tuning observed in biological cochlea.Considering the need to develop fully implantable cochlea in the near future,this paper will try to design a bio-realistic analog CMOS cochlea filter with low power consumption and small area.Firstly,this paper analyses the intrinsic frequency response of the biological cochlea to establish the optimal filter transfer function,and then selects the lowest power consuption Gm_C structure as the basic filter structure.Secondly,after analysing different types of Gm unit,a modified two sides input and single output which is suitable for low power consumption is utilized as the OTA of the filter.Finally,a ninth-order CMOS cochlea filter with a adjustable center frequency ranging from 20 Hz to 12 KHz is presented.By making all MOS transistors work in the subthreshold region,using active resistance and single output OTA structure,the chip area and power consumption is greatly reduced.In addition,A low-voltage low-power CMOS reference is built,while the cochlea filter tuning system is also design according to the feedback control mechanism of the biological cochlea.At last,the filter layout is accomplished with the reference of the standard layout design rules.The filter is implemented in SMIC 18.0?m CMOS process and 1.0 V power supply is adopted,the active area of single filter channel is20264.0 mm,and the powerconsumption is as low as 3522.0nw.Simulation result show that the center frequency of the filter can be tuned between 20Hz-12 KHz by adjusting the bias current of the Gm unit,the peak gain of filter channel can reach 34.05 dB while the roll-off slope steepness maintains over 300 dB/dec.The proposed analog CMOS cochlea filter is able to behave similarly to a biological cochlea with low power consumption and small area.