Research On Analog Front-end Circuit For ECG Signal Acquisition System

The rapid growth in low-power integrated circuits, wireless communication and physiological sensors has enabled a new generation of wireless sensor networks(WSN), now used for purposes such as monitoring traffic, crops, infrastructure, and health. The wireless body area network(WBAN) field is an interdisciplinary area which could allow inexpensive and continuous health monitoring with real-time updates of medical records through the Internet. A number of intelligent physiological sensors and chips can be integrated into a wearable wireless body area network, which can be used for Bio-signal Extraction and early detection of medical conditions. The sensors and chips used in WBAN would have to be low on complexity, small in form factor, light in weight, power efficient, easy to use and reconfigurable. The Analog Front End circuit(AFE) for signal acquisition system is very sensitive to system noise, power line interference etc., it has always been a key restriction in power consumption and chip processing accuracy. This thesis focuses on the design of Analog Front End circuitry for Electrocardiogram(ECG) signal acquisition system.This thesis firstly describes the characteristics of biomedical signals, mathematical models of bio-potential electrodes, power line interference and system noise sources, and on the basis above, the specifications of AFE is derived. Based on the system power consumption, area and design complexity analysis, the system consists of an electrode DC offset removed band-pass(BPF) low-noise operational amplifier(LNA), a Sinc-shaped anti-aliasing filter, and a low power oversampling successive approximation register analog to digital converter(SAR ADC) is proposed. A symmetrical pseudo-resistor is proposed to achieve high linearity and high resistance, Combined chopping technique, source degeneration technique, current-split technique, transistor bias voltage and transistor size optimization, a low offset, low noise and low power amplifier can be achieved. By using oversampling design method, the anti-aliasing filter design can be achieved by an open-loop Gm-C integrator and periodically reset switches, and the process of charge sampling(integrate-and-dump), results in a Sinc-shaped frequency response with deep notches placed at fs and its multiples, which satisfies the frequency response of anti-aliasing filter. the operational transconductance amplifier use negative feedback loop to improve its linearity and input range. Finally, the low-power SAR ADC is designed by using capacitance-split Vcm-based switching procedure, dynamic comparator, and dynamic control logic.The prototype was fabricated in SMIC 0.18μm CMOS technology. The measurement result shows that the low noise operational amplifier exhibits a band pass frequency response characteristic. The cut off frequency are 0.45 Hz and 200 Hz at low and high end respectively, and the mid band gain is 39.2d B. The amplifier exhibits 2.4μV offset voltage and 1μVrms input referred noise, hence the Noise Efficiency Factor(NEF) is 2.16. When around 80 Hz input signal is applied, SAR ADC achieves 58.3d B SNDR and 9.39 bit ENOB. The system works under 1V supply, dissipating 2.8μW power, and exhibits 1.4μVrms, and occupies 1mm2.