The Implementation Of The Infrared Image Preprocessing Algorithms On FPGA Whose Resource Is Limited

With the development of infrared focal plane array imaging technology and infrared focal plane image processing technology continuing to mature, the infrared detector array and the frame rate are increasing constantly, which has brought great challenges to the real-time processing of the infrared image. The traditional processing method has been difficult to meet. FPGA has strong flexibility and parallelism, suitable for modular design. At the same time, FPGA needs short development cycle. Also, it is easy to maintain and expand, which is suitable for real-time signal processing. So using FPGA to do real-time image processing is a good choice.Firstly, this paper analyzes the nature of non uniformity of band in infrared focal planeimage. We use the single direction of the total variation to capture the image noise, and set up the energy functional with gray domain containing data fidelity term. Then we use split Bregman iterative optimization to solve this problem. The experimental results show that the algorithm can effectively remove the strip and preserve the details of the image perfectly. Also, the algorithm has good stability for the random noise and the parameters.Secondly, for the characteristics of the single direction total variation correction method, two iterative models, data stream driven iterative model and memory iterative model are proposed. According to the practical application environment, the data stream driven iterative model is used for the FPGA design, which can process the real-time images.Finally, based on the characteristics of dim targets in the background of sea in infrared imaging, a variety of infrared dim target background suppressing algorithms are studied and discussed. By contrast, lateral Inhibition algorithm has good effect in the application scenarios of this paper and easy hardware implementation. In addition, this paper also realizes the algorithm on the FPGA platform, and verifies the effectiveness and stability of FPGA implementation. A detailed analysis of the implementation of the FPGA algorithm of resource usage and performance is proposeed.