| CMOS image sensor(CIS) has developed greatly since it was invented, and has been widely used in the field of consumer electronics, medical, aerospace and military. With the developments of CMOS process technology, the power consumption is reduced significantly while the area and supply voltage of CIS have been lowered to a certain level. In the future, the low-voltage and low-power CIS will be an important research trend in the field of CIS. As the transform media between analog and digital part, the performance of ADC determines the imaging quality of the CIS. ADC is an essential part of the CIS readout circuit. The research of the low-voltage Column-Level ADC has become the key part of the study of the low-voltage and low-power CIS.In order to realize high resolution conversion of the ADC in CIS, this thesis employs two characteristics of the Σ-Δ ADC---oversampling and noise shaping. Based on the traditional Σ-Δ ADC, the incremental Σ-Δ ADC is studied which is applied to CIS. Meanwhile, beginning with the derivation of the basic theory of the 1st-order structure in frequency domain and time domain, the conversion features of the ADC is further analysed and the structure is extended. By comparing the 2nd-order and the 3rd –order structure, the 2nd-order incremental Σ-Δ ADC structure is chosen as the ADC which is used in CIS in this thesis. With consideration of both the system stability and the nonideal factor, the circuit parameters are chosen. Furthermore, in order to satisfy the requirement of low-voltage modulator, the supply voltage and power consumption is degraded effectively by employing a gain-boost class-C inverter to replace the traditional OTA in this research. Based on the incremental ADC, the auxiliary SAR ADC is added. By dividing the conversion process into two steps----coarse conversion and fine conversion, the necessary clock cycle is reduced and the converting speed is improved.The incremental Σ-Δ ADC is realized in a SMIC 65 nm CMOS process, and the simulations has been taken in 1V supply voltage. The results show that this ADC achieves 80.4 dB SNDR, 13.01 bit ENOB and 0.726 LSB max INL, and that the power consumption is 25μW. The improved ADC is designed in CMOS process, and it operates in 1.2-V supply voltage. The results show that this ADC achieves 81.26 dB SNDR, 13.21 bit ENOB. The necessary clock cycle is reduced to 100 cycles while the incremental Σ-Δ ADC needs 200 cycles, although they have almost same resolution. |
