Simulation Study On Single Event Effects Of FinFET-based SRAM

In pace with the speedy development of national defense as well as military cause, the problems in IC chips are becoming more and more serious and the reliability studies on electronic devices and chip system are important. From a long-term perspective, the harden of radiation effect research maybe produce impact factors on semiconductor industry and hinder its development. For example, when a electronic devices developed we first test it reliability of radiation and in the process of design system we set its hardening of radiation as important goal. Because of the various limitations of in the lab it's very hard to make the space radiation effect experiment, so it's make good sense to do computer simulations. The simulation conclusion can also provide reference on study of electronic devices and design of system.This article through the simulation analysis of single event effect(SEE) of Fin FET device and come up with research results as following:1. We introduce the principle of operation and advantage of Fin FET and use Sentaurus TCAD to construct3 D model of Fin FET device and simulates SEE of this device under the striking of heavy ion with different energy based on the heavy ion striking theory model. The result shows that there is a drain pulse current after the heavy ion striked in drain. Its reason is that heavy ion will deposit energy in the penetrating path and generate quantities of electron-hole pairs that will form a current when separated by an external electric field. The current is consistent with double exponential pulse current and increase with particles LET values.2. Through analysis and draw some conclusions: Silicon Fin FET is better than planar MOSFET in hardiness of SEE due to its small sensitive body; For SOI and silicon Fin FET, SOI is far superior to silicon structure in hardiness of SEE because existing buried oxide blocks charge generated in substrate so it cannot be collected by drain; We can weaken the parasitic bipolar amplification effect by increasing source voltage and shorten fin height decreasing the particle track path for increasing the hardiness of SEE. Through analysis we found that the bipolar amplification effect cannot be neglected and we use bipolar gain ? to evaluating it. We also found that ? is nonlinear increase with the fin height and ? of SOI is about 1.36 times as silicon structure.3. We use Hspice to design Fin FET-based SRAM cell for hardiness of SEE. Firstly, we briefly introduce the BSIM-CMG model which is a standard Fin FET model. Next, we propose five different kinds of SRAM cell based on the theory that improving source voltage may weaken the parasitic bipolar amplification effect. Finally, we make a comparison type A and type E on ability of hardiness of SEE and analysis those SRAMs' on static noise margin, read noise margin and write noise margin providing a basis for designing SRAM with hardiness of SEE.