Design And Research On Mixer Of The Navigation Receiver

The Bei Dou Navigation Satellite System is a Chinese self-developed global satellite navigation system. Undoubtedly, its construction and improvement will play a huge role in advancing social and economic development.The receiving terminal on the ground is of great importance in the system.A mixer functions as a significant component of the receiver in the BDS, and itsperformance will directly determine the overall performance of the receiver. Consequently, it is of great significance to study the design method of the mixer module in the receiver.A quadrature mixer which employs folded double-balanced Gilbert structure was implemented in TSMC0.18μm RF CMOS process library. Compared with the conventional Gilbert cell, this mixer has many advantages. The folded switch stage is used to improve the isolation between the ports. The active load comprised of a current source improves the conversion gain of the mixer. Besides, the common-mode feedback circuit, which is used to create a stable operating point for each key node in the circuit, can thus improve the linearity of the mixer. What’s more, the I/Q shared input stage can not only mix the in-phase and the quadrature phases but also decrease the power consumption of the circuit.At the beginning of this thesis, the basic theoretical knowledge of receiver and mixer is presented. During thecircuit design of mixer, the theory of conventional Gilbert Cell mixer is analyzed and a folded double-balanced active mixer is proposed by optimizing and improving the conventional one. The following part shows the theory analysis of conversion gain(CG) and noise figure(NF) in the folded double-balanced active mixer in detail. Deducing of the key parameter that affect the CG and NF is shown next. The third part is the confirming of the overdrive voltage and transconductance of MOSFETs according to the relation between transconductance efficiency and overdrive voltage and the influence of MOSFET’s parameter on gain and noise and also the channel length of MOSFET through analyzing the impact of process and MOSFET’s parameter on the performance of mixer. Furthermore, the design of common-mode feedback(CMFB) circuit that providing stable common voltages for every key nodes in the mixer is presented. Finally, this thesis presents the pre-simulation, design verification of layout and post-simulation results of the designed mixer.In this thesis, the pre-simulation, layout design and post-simulation of the mixer are carried out with the help of Advanced Design System(ADS)and Cadence Design System. ADS software simulation results show that the conversion gain of 24 d B and the noise figure of 9.3d B can be obtained at the RF input frequency point 1.561 GHz. Moreover, the IIP3 is-19 d Bm and the isolation is greater than 150 d B. The current consumption of the chip is 3.8m A at a supply voltage of 1.8V. The pre-simulation results show that the mixer designed in this thesis can meet the system requirements. Based on the Virtuoso software, the mixer chip is with an area of 230um×320um. The post-simulation results show that the conversion gain of 22 d B and the noise figure of 11 d B can be obtained. Moreover, the IIP3 is-18 d Bm and the isolation is greater than 70 d B. The current consumption of the chip is 3.8m A at a supply voltage of 1.8V. The major reason for the change of the simulation results is that the parasitic parameters of the layout can influence the simulation performance.