Testbench Design And Implementation For Video Input Module Of Display Control Based On UVM Verification Methodology

With the increasing integration of the chip, the RTL IP level functional verification of the early stages of the IP is more and more significant to guarantee the correctness of the whole chip design and shorten the design cycle.However, because of the poor scalability and reusability of the structure, the traditional direct verification method has become more and more prominent, and the random verification method based on System Verilog has become the mainstream verification method. The verification methodology developed by System Verilog language, the UVM verification framework is widely used in many large IC design companies.The main function of video input module of display control of Graphics Processing Unit(GPU) is to receive the external input video data, extracting the effective video data and processing it,and then outputing the data to the MMU, then the video data is read and processed by the video output module of display control. With traditional direct verification method to verify the control signal input module, it is difficult to practice effectively frame data and fault modeling, and to verify the correctness of the results of the analysis is very complex. In addition, the use of lower efficiency of conventional direct verification method validation and verification coverage is not guaranteed. Therefore, to improve verification coverage, shorter verification cycle, the use of more advanced verification methods is necessary.In view of the above problems,this thesis is based on the UVM verification methodology to develop a verification scheme to verify the input module,building a verification environment based on UVM.The platform architecture is redesigned to increase the cpu_env environment coordinate with display_env,which is used to configure the initial value of the relevant registers in the DUT and the reference model at the beginning of the simulation.UVCs has a large number of functional optimizations and increases.In the TLM,developed three kinds of TLM modeling for the stimulus generation,register initial value configuration and Data comparison.In vi_driver, implemented data driven in TV or VESA timing. In vi_modle,used System Verilog language writing the YCb Cr to RGB function,TV time and VESA timing function and the line buffer error processing functions,so as to achieve a complete simulation of the RTL function.In vi_scoreboard,realizated of non_synchronous compare,error tolerance mechanism and comparison error stop function.In verification process,extracting the function point of the input module,realizing the Transaction Level Module,and writing large number of complex sequence and coverage collecting code for verification.and finally many functional errors were found,the statement coverage,the branch coverage rate reaches more than 98%,the functional coverage rate reaches100%.Based on UVM verification methodology,which is suitable for the complex So C functional verification,which saves more time and energy,which reflects the basic idea of UVM verification methodology.