Simulation And Verification For Master Device Based On PCI Bus

With the rapid development and the widespread application of the large scale integrated circuit technology, there are more and more requirements to the functions of the integrated circuit, clock frequency, power consumption and stability. Among them, the correctness of the circuit functions is not only the most basic but also the most important requirement, the verification for integrated circuit is a key way to ensure the correctness of its functions. In this paper, it mainly focuses on the study of the functional verification for the master devices in the PCI host interface module, which is based on a project of the graphics processor unit. PCI host interface module is the external communication interface of the graphics processor unit, which has an internal integration of two master devices, a command processor and a directional memory access controller. These two master devices realize the data transmission and data analysis between the graphics processor unit and the external host through a PCI bus transmission operation. The master devices play an important role, like a data entry, in the graphics processor unit, therefore, it is of great significance to carry out a completely functional verification for each master device.First of all, this paper makes a profound analysis of the functions of the command processor and the directional memory access controller, in order to extract the basic functions of the two modules under test. Secondly, by combining the existing design codes of the two module, the testing items for each function point is planned, including the specific types of the PCI bus transmission operations. Thirdly, considering the requirements of the verification environment construction, three different types of data files in binary code is created, which are essential in the operation process initiated by the master devices, meanwhile developing the fundamentally functional modules of a memory management unit and a image processing subset, which are interactive with the master devices. Fourthly, it is important to construct a platform for verification of the modules under test in the Linux environment, to do the interconnections between the modules and the adjustment for the platform, to compose the operation scripts for the automatic verification platform and to select the combining methods of the dynamic orientation verification and random verification as a validation way for the module under test, then according to the verification plan table, there are 59 testcases developed in total,50 of them are for the command processor and the rest of them for the directional memory access controller. Finally, through the simulation tools, the work of simulation and verification is implemented respectively and fully for the command processor and the directional memory access controller, observing the simulation results and recording the code coverage of the master devices after completing verification. Eventually, it is essential to make a conclusion based on the code coverage through analysing and refining.By observing the simulation results, it is helpful to make some reasonable modifying and increasing or decreasing for some of the testcases as well as the multiple regression verification, finally the statistics show that the functional coverage rate reaches 100%, the overall code coverage of the command processor reaches above 96%, the overall code coverage of the directional memory access controller reaches above 95%, which meets the requirements of the functions and verification.