The Research And VLSI Implementation Of HEVC Inter Prediction Decoder

As for the existing H. 264 standard can't meet the high-definition resolution video real-time transmission and broadcast requirements, the international JCT-VC organization develops and publishes a new video encoding standard High Efficiency Video Coding(HEVC). In the case of similar coding quality, HEVC has the obvious increase to H.264 on coding efficiency, and the rate of HEVC can save nearly 50%. But with the increase of video computational complexity and the amount of data, HEVC software decoding is difficult to meet the needs of real-time decoding. For HEVC inter-frame decoding is one of the most time-consuming modules in the decoder, it needs to design a special hardware acceleration unit to meet the high resolution and high frame rate decoding performance requirements.According to the analysis and actual demand above, this paper studies and designs the HEVC inter-frame decoding and its special hardware acceleration module:It is significant to study on the HEVC standard protocol and analyze the code flow structure. For the HEVC software model HM 12.0 motion compensation and the adaptive optimization algorithm of motion compensation, the paper carries on the thorough research on the Merge mode technology, advanced motion vector prediction technology, the Skip mode prediction technology based on the Merge mode, sub-pixel interpolation filtering technology and weights of pixel processing.Combined with the hardware circuit design rules, the paper puts forward the VLSI design architecture and modules of the HEVC inter-frame decoder. In order to improve the parallel execution performance of the hardware acceleration circuit and the efficiency of decoding, it determines to use the pipeline technology in the overall architecture. On the modules design, it comes out some key technologies, such as parallel processing of sub-pixel interpolation, parallel processing algorithm of the prediction, scalability of reading reference pixels and the classification storage of motion information.The paper builds the simulation platform for the designed inter-frame hardware acceleration decoding module to complete the debugging and analysis of the design. The simulation result shows that the designed HEVC inter-frame hardware acceleration module conforms to the requirements of the decoding of high performance and high-definition video. And the data performed by the hardware decoding module consistent with the data from the software.Based on the research of the inter prediction technology, this paper implements the inter-frame hardware accelerated decoding module. The advanced technology is embodied in the following points: on the one hand, the inter-frame decoding is realized by using special hardware unit. On the other hand, it uses some efficient design methods like parallel processing and scalability to read the reference pixel.