Research Of Dual Channels Pipeline-SAR A/D Converters

The continuing demand for ever-higher wireless data rates has resulted in the definition of higher-bandwidth wireless standards such as LTE-advanced. Wireless receivers for these standards require converters with at least 50 MHz of bandwidth,with ADC specification of 100 MS/s of speed and at least 8 bits of effective resolution. Moreover, a faster, more accurate converter can be leveraged to relax the analog signal conditioning in the receiver, by reducing the requirements for anti-alias filtering through oversampling or increasing the robustness to out of band signals through improved dynamic range. In this work we target a converter with 12 bits of effective resolution and a 160 MS/s speed. As in a handheld device power consumption is critical, the converter must be optimized for energy efficiency. By ensuring the power consumption scales with the clock frequency,power can be saved while receiving lower bandwidth standards.Conventional implementations for converters with these requirements are mostly pipeline converters. However, the amplifiers in those converters usually consume significant amounts of power, reducing the energy efficiency. On the other hand, SAR ADCs have reached energies efficiencies below 10 f J, but only at rather low sampling frequencies or moderate resolution. Elements of both pipeline and SAR architectures can be advantageously combined, where two energy-efficient SAR converters are pipelined for higher speed. The power required for residue amplification is limited since this architecture only requires one amplifier, and this power is further reduced by sharing a single residue amplifier between two interleaved channels.The proposed ADC is achieved with SAR-Pipelined structure, which merges SAR ADC and Pipeline ADC effectively and System level analysis of the SAR- Pipeline ADC is proposed, the non-ideal effects in Pipeline-SAR ADC discussed with corresponding solutions.A 100 MS/s, 12 b SAR-Pipeline ADC is achieved, on the basis of which a 160 MS/s, 12 b dual channel time-domain SAR-Pipelined ADC is implemented with time-domain mixed structure and channel.The sample-time error among channels, gain mismatch and offset mismatch are analysised in some detail and the digital calibration is introduced according to the mismatch.The prototype was fabricated in TSMC 65nm CMOS technology, The results of the circuit simulation show that the pipelined SAR ADC achieves 90.63 d B SFDR, 71.89 d B SNDR and 11.65 bit ENOB from 1.2V power supply at 160MS/s,with a power dissipation of 45.3m W.