A System-level Verification Of Clock Data Recovery Based On UVM

Along with the accelerated development of digital integrated circuit, increasing scale of design, more complicated products and increasingly reduced design cycle, there have been more difficulties in verification. Meanwhile, the time spent in verification accounts for a large proportion in design cycle. On one hand, the advanced verification method could enhance working efficiency. On the other hand, the correctness of integrated circuit function could be guaranteed.The common verification methodology UVM based on System Verilog integrates features such as OOP, dynamic thread and cross-thread communication. In the meantime, it also brings some unique features including restraint and function coverage to the verification. As a result, the efficiency and quality of verification is enhanced. The framework of UVM and the functions of its main components in the platform are analyzed in this paper. Meanwhile, how the mechanisms such as congfig db, phase and sequence work in the platform and the communication connection interface among each component of UVM is studied.The verification object in this paper is Clock and Data Recovery module in DSP chip. Building verification platform of Clock and Data Recovery module based on UVM verification methodology is the research core of this paper. The module’s function and methods for logical realization and division of function points are analyzed in allusion to the framework of clock data recovery system and based on development standards and demands. Through comparative analysis of the studies carried out at home and abroad through traditional verification method Verilog language and advanced verification method VUM based on system Verilog, UVM verification platform is designed for Clock and Data Recovery module. Through introduction of three agents, simulation stimulus is generated and driven, the intermediate and final output results are collected respectively. By building the library, the test cases of regression are introduced. The completeness of verification is guaranteed by adopting the coverage-driven verification process. The starting sequence in the platform is managed and the scene of case building and the system verification of clock data recovery module are completed through virtual sequence. The result indicates that the system verification platform of clock data recovery module based on UVM verification methodology uses a few verification cases, shortens the verification time and enhances verification efficiency and completes the verification task. Ultimately, according to the coverage report, code and expression coverage reaches above 95%. The function coverage reaches 100%. As a result, the project requirements are satisfied.