Design And Verification On DSP Frame Synchronization System For 100Gbps Optical Transmission

With the exponentially growing internet video applications, big data, and cloud computing during recent years, the optical transport network of backbone has been continuously pressed, and the backbone network lacks power. To cope with the pressure from the increasing data flow, the 100 Gbps transportation system with OTN exchange technology has been gradually put into business. As the core technology of 100 Gbps system, the 100 Gbps digital signal processor must address the data processing issues in the optical transport process(Throughput 128Gbits/s). The performance of the DSP directly determines the load capacity of the 100 Gbps system, therefore the 100 Gbps digital signal processor chip is extremely important for 100 Gbps transportation system.As the OTU4 business information is received from client side, 100 Gbps digital signal processor is mainly used PDM-QPSK modulation scheme to process it with the method of FEC encoding, differentially encoding, inserting the training sequence, and conducting QPSK modulation, and then the information is sent to the line side. At the other line receiving side, the analog electrical signal is received by using coherent optional demodulation receiver technology, and goes through high-speed ADC for digital-to-analog conversion. Then use the processing of digital coherent demodulation and FEC decoding to recover the client-side information.This paper studies the realization of 100 Gbps DSP frame synchronization system, and focuses on in-depth research on functional structure of the frame synchronization system of 100 Gbps DSP chips. The frame synchronization system completes header differential decoding, correlation detection to find header, lane adjusting alignment, large frequency offsetting compensation、the removing the QPSK phase ambiguity etc. The method of synchronization mainly takes advantage of the known sequences to conduct correlational computation and find the user-defined headers. Since the four XI, XQ, YI, YQ headers are different, which can distinguish four lanes. According to the known information of the headers to complete alignment of four signals, and according correlation peak to determine whether large frequency deviation will happen, sending +8G or-8G to the frequency offset estimation and compensation. Removing phase ambiguity is completed by inserting known training sequences, at the same time the inserted headers and trainings sequences of four signals are deleted to complete the processing of the frame synchronization system. Then according to the functional requirements of each module, use a top-down approach with hardware description language to complete the designs of frame synchronization system of each module. These designs make an innovative especially in the header search for a sliding window design, data stream synchronization caching processing design and CSRZ correct design to reducing the hardware resources. At last, a simulation platform of UVM is used to verify the function of frame synchronization system and give key testcases, and the result of simulation shows that this design addresses all the requirements of frame synchronization system.