Designs And Researches Of Low Power Successive Approximation Analog To Digital Converter

As technology scales, the improved speed and energy efficiency make the successive-approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/Reference voltage settling.A 10-bit 50Msample/s Pipeline ADC, which is based on switch-embedded opamp-sharing architecture, is fabricated in CSMC 0.18μm,1.8V supply voltage mixed signal CMOS technology. The design specifications of input signal are as follows, the common voltage is 950mV, the input range is from -900mVto 900mV. The measured ENOB achieves 7.6-bit, SFDR is 52.2dB and SNR is 47.3dB.This thesis focuses on the theatrical analysis and circuit design of low-power SAR ADC. The main innovations of this thesis are as follows. (1) This thesis provides an improved merged capacitor switching (MCS) scheme, in improved MCS scheme, the final unit capacitor should be switched according to the previous quantification result. Compared to the MCS procedure, the switching energy and total capacitance are reduced by 70% and 50%, respectively. (2) For the purpose of illustrating the advantage of power consumption in improved MCS scheme, detailed calculation process of switching energy of a 3 bit SAR ADC, which adopted improved MCS scheme, was provided. (3) An improved detect-and-skip (DAS) is provided in this thesis to improve the sampling rate. The improved DAS scheme which sets the fine DAC switches immediately after each coarse DAC SAR bit decision. (4) In order to provide the limitation caused by capacitor mismatch and noise introduce by sampling switch. The specific analysis of capacitor mismatch and noise is provided in this thesis. As a result, compared to merged capacitor switching scheme (MCS) procedure, the average switching energy and total capacitance of SAR ADC, which is designed in this thesis, are reduced by 80.585% and 47.6%, respectively.Based on the improved MCS scheme and improved DAS scheme, a 10-bit 50Msample/s SAR ADC prototypes were designed in SMIC 0.18μm 1P6M mixed signal CMOS technology. The common voltage of input analog signal is 900mV, the range of input analog signal is from -1.6V to 1.6V.