Optimal Design Of A ∑△ Fractional-N Frequency Synthesizer For UHF RFID Systems

The rise of the internet of things promotes the development of wireless communication system,among which UHF RFID technology stands out and pushes the application of the readers.Frequency synthesizer, as one of the critical modules, is used as frequency conversion in the transmitter and receiver, which determines readers’ tag reading efficiency in the complex environment to a large extent.A ∑-△ fractional-N frequency synthesizer is designed according to the transmitter’s and receiver’s requirements for phase noise in the UHF RFID readers. The loop parameters and technical indexes of each module are summarized in this paper based on the analysis of the noise characteristics, including the loop bandwidth, filter parameters, charge pump current, VCO gain and so on. Meanwhile, the behavior level simulation is adopted to verify the rationality of parameters.The circuits of a phase frequency detector(PFD), a charge pump(CP), a voltage controlled oscillator(VCO), a programmable divider, a sigma delta modulator and an automatic frequency calibration(AFC) are designed and implemented in this paper. The traditional three-state structure with a delay unit is used in the PFD to eliminate the “dead zone”. A folded-cascode amplifier is employed in the CP for the compatibility and the adjustability of the current. Simulation results show that the CP current is adjustable from 95μA to 123μA and the matching degree of charge and discharge current is 84%. A complementary cross-coupled topology with a switched capacitor array is adopted in the VCO to balance the tuning range and phase noise. The programmable frequency divider is constituted by six divide-2/3-units, which are composed by the high-speed current mode logic(CML) latches based on the cross coupling topology with negative resistance characteristics.Simulation results indicate that the divide ratio is between 64 and 127 with step of 1. A novel AFC circuit is proposed in this paper to choose the optimal tuning word of VCO and to reduce the lock time based on the successive approximation algorithm.The die area including the entire pads is 1495×1059μm~2 in the SMIC 0.18μm CMOS process.The post-simulation results show the locking time is less than 35μs at the I/Q output clock frequency of 860MHz~ 960 MHz, and the whole power consumption of 30 mW is achieved at the supply voltage of 1.8V.