Design And Research Of External Memory Interface For General Purpose Reconfigurable Computing

General purpose reconfigurable computing is a new direction in the research of computing architecture. The object of reconfigurable computing will evolve into multi-domain because of the balance of the demands in mounts of applications. At the same time, the speed of memory access will become the bottleneck of the computing performance when facing the domain with high degree of parallelism. So it’s necessary to design an external memory interface to improve the performance of general purpose reconfigurable computing system by improve the usage of memory bandwidth.According to the research in classifying the exist algorithms by Berkeley University, this thesis selected and studied some algorithms from the memory access limited classifications in order to guide the optimizing of external memory interface facing general purpose reconfigurable computing. After that, this thesis get the feature of data location and the sequence of data address from critical algorithms by a simulation tool. With the data location, this thesis summarized three kinds of data locations which are linear data location, block data location and jumping data location and designed a multi-mode reconfigurable bus. With the sequence of data address, this thesis discovered the repeatability of the data flow with stride prefetching feature and optimized the stride prefetching solution.The verification is implemented in RTL simulation platform and FPGA platform. The outcome of RTL simulation platform shows the multi-mode reconfigurable bus is 46% better than AHB and the optimized stride prefetching solution is 7.4% better than other stride prefetching solution. The consequence of FPGA platform demonstrates that the throughput of writing data is 6.5Gbps, the throughput of reading data is 10.3Gbps and it meets the demand.