Design Of 24-BIT 48KSPS Multibit Quantization Σ-Δ ADC

Σ-Δ ADCs gain popularity in the field of high-precision analog to digital converter for its relatively lower analog circuits complexity and good compatibility with digital circuits. Besides the accuracy requirements, how to optimize the circuit configuration to lower power consumption has been a hot topic in the analog field.First, this paper introduces the Σ-Δ ADC hot topics and major constraints, the latest development and research at home and abroad have also been summarized and analyzed. Then the dynamic characteristics of the Σ-Δ ADC are explained in detail, as well as the principles of oversampling and noise shaping technology which help to improve the system SNR. Take a first-order modulator as example, the paper illustrates the Σ-Δ ADC works, and discusses the advantages and disadvantages of higher order structure and multi-bit quantization structure. After analysing of the transfer function of the modulator, 4-order 17-level quantization feedforward modulator is seleceted,the oversampling rate is 64. By optimizing the feedforward branch, including reducing the number of input branches of the summaation network, increasing the first-stage integrator gain coefficient, the load of the modulator is reduced. The influence of non-ideal characteristics of the critical modules are discussed, including amplifiers, sampling switches and capacitors,nonlinearity introduced by the feedback DAC, and the system stability is also analyzed. Through applying complete behavioral simulation, the performance characteristics of the critical circuit modules are obtained. A transistor-level switched-capacitor modulator circuit is designed in which the digital correction logic DWA(Data Weighted Averaging) for the multi-bit quantizer is written in RTL code. The modulator digital output is send to a 5-stage digital filter which perform filtering and down-sampling processing to derive the 24-bit 48 kSPS final output. The system supply voltage is 5V, with a 3.072 MHz sampling clock, the signal bandwidth is 24 k Hz, the simulated SNR is 123.1d B, dynamic range achieves 127.9d B, and total harmonic distortion is below-125.5d B, total power consumption is 10.12 m W.The design is implemented in BCD350 GE technology, wherein the analog layout is designed with full-custom, and the digital layout is realized by automatic tool, the core size of the final layout is 1037.51μm×1084.895μm.