Low Power Design Of Variable Dynamic Range Second-Order Sigma-Delta Modulator

In the field of analog to digital conversion, Sigma-Delta ADC gets high conversion accuracy through digital signal processing, thereby reducing the performance requirements of the analog circuitries in the converter. For ADC with given quantization noise, the output signal-to-noise ratio increases with the input signal magnitude. In practical applications, the ADC worst output signal-to-noise ratio, which corresponding to the minimum input case, must meet the SNR specification. When the input signal is larger than the minimum case, the output SNR is larger than requirement, which means unnecessarily extra power consumption. In order to improve this situation, this thesis proposes a reconfigurable Sigma-Delta ADC which can be used in an adaptive system. The system can choose ADC conversion accuracy according to the system requirement, avoiding the unnecessary output SNR surplus, thus minimizes the system power consumption.In this work, various non-ideal factors of the second-order Sigma Delta analog modulator were first mathematically analyzed, and then the non-ideal models were built under matlab SDtoolbox. The effects of non-ideal factors, which include finite operational amplifier gain and limited bandwidth, integral capacitor mismatch, clock jitter, thermal noise of switches and operational amplifiers, etc., on output SNR have been studied by numerical simulation. Based on these analyses, for a given operating condition including amplitude and frequency of input signal, over-sampling rate(OSR) and the output signal-to-noise ratio(SNR), the specifications of ADC building blocks including operational amplifiers, switches and sampling capacitor have been calculated automatically.Based on CSMC 0.5 um CMOS process, under the 5V power supply voltage, we designed a reconfigurable second-order Sigma-Delta modulator. With varied ADC accuracy requirements or varied input signal magnitude, the specifications of the modulator building blocks have been computed automatically by a specification allocation algorithm developed in this work, and the internal circuit reconfiguration have been realized by controlling internal switches. The simulation results show that under 2.5MHz clock, the quality factor of half input system is 6, which is better than the traditional design. The results show that by changing the structure of reconfigurable parts of the modulator, the output signal-to-noise ratio of modulator can be adjusted, and at the same time system power consumption can be minimized.