SoC Low Power Design And Implementation Based On Multi-Bit Flip Flop

With the rapid development of semiconductor industry and the reduction of the process dimension, SoC(System on Chip) integrates more logic circuit in one chip, and nowadays the power problem in chip design influences chip performance, package refrigeration and equipment reliability, therefore, the low power design is another factor to consider when design engineer evaluates chip area, cost and performance.In the current integrated circuit design, widely used and effective include: multi threshold voltage technology, power switch technology, clock gating technology, netlist optimization technology, and multi voltage supply technology. When the chip is working, the dynamic power accounted for 90% of the total power, dynamic power consumption on the clock path accounted for 40%. Based on a SoC design which need low power, this paper is certain to use clock gating technology, gate level power optimization and multiple power to reduce chip power. But the result can not meet the standard. At last, after analysis of logical function, we designed the multi-bit( multiple bit) flip flop cell and use it in the chip design instead of the commonly used flip flop which is single bit. This can effectively reduce the dynamic power consumption and cell area. With its help,the chip total power can meet the standard at last.This paper optimize the multi-bit flip flop in order to make it can be effectively used in the chip design which should not violate design rules under the new technology, we mainly discussed as follows:First of all, use the clock reuse method it to design multi-bit flip flop circuit and GDSII layout. And use tools to extract parasitic parameter( include resistor and capacitance) which is used to analysis the performance of multi-bit flip flop. After studying the structure of multi-bit flip flop, the cell library including power and timing information is customized.Then according to the flow of chip design, it need to add multi-bit flip flop in the chip logic when compile chip netlist, fix design rule violation when place and routing standard cells. And at last stage, we should confirm chip logic function is consistent with the initial RTL, then analysis chip timing and power.At last, by the use of independent design of multi-bit flip flop technology combined with other low power technology, power consumption was reduced by 36%,up to the initial 35% standard.The research of this paper has made good progress and applied to the design of actual project.