The Parameterized Design And Verification Of The On-Chip Shared Cache

Currently, CMP has become the mainstream of the development trend of the processor. As an important part of on-chip memory hierarchies of CMP, the on-chip shared cache plays a key role of the performance of the system. The parameterized design of on-chip shared cache is an effective way to enhance the system reusability and extensibility. O n the background of a high performance microprocessor FT-MX designed by National University of Defense Technology, this paper has implemented the parameterized design and verification of the on-chip shared cache, the main work of this paper is as follows:First, analyzed the general design methods of on-chip shared cache in CMP, then studied on different non-blocking caches and miss pipelining, we designed and implemented an on-chip shared cache with non-blocking pipeline structure, which reduced the memory access latency caused by cache miss effectively and improved the overall performance.Second, studied the general parameterized design methods of on-chip shared cache. According to the application demands, we implemented the parameterized design of the shared cache. This parameterized shared cache supports a total of eight kinds of configuration schemes among capacity, set associative degree and bus width with the L1 Cache line width. The capacity of the shared cache can be configured with 512 KB, 1MB. Set associative degree in 4-way, 8-way can be configured.Third, we verified the shared cache from Model-based verification and directional verification two aspects. Through generating constrained random stimulus, the automatic comparison mechanism and coverage analysis, we verified the shared cache full and completely.At last, we carried on logic synthesis for the shared cache under the 40 nm process of a certain manufacturer. After repeated re visions and optimization, the working frequency meet the 1GHz, the area and power consumption have satisfied the design requirements.