Development Of Automatic Test System Of An Electronic Control System And Research On SRAM Built-in Test Method

This paper consist of two parts,the development of an automatic test system and research on SRAM built-in test method.Firstly,the electronic control system plays a key role in a large scale and complicated digital equipment,so it is necessary to test its functional features,performance characteristic and fault conditions.BIT(Built in Test)technology and AT(Automatic Test)technology take an important role in this area.However,this technology faces low diagnosis ability and high false alarm rate,which severely affect the credibility of its diagnosis.Therefore,testability work usually be done by R&D institutions independently,lack of unity,normative and generality.Hence,after considering the current situation,this paper will carry out the following research:(1)Previously,according to hardware testable points,people established test items,but this method isn't general.In this paper,I divided the digital controller into six parts and based on the characteristic of BIT design of each function module,and then establish automatic test items.(2)Development of an automatic test platform in an automatic test equipment with CPCI cards,which is used for measuring the diagnostic capacity of BIT modules.At the same time,in order to reduce development period,cut down the research cost and raise the cost of maintenance with regard to the other congeneric automatic equipment.In addition to,developing class driver software so that class driver can separate upper UI and device driver,and this method possesses highly portability.(3)Due to the high proportion of the memory area,this paper is mainly focus on the fault models and test algorithms.For each kind of single faults and couple faults,I summarize it's the most simplified algorithms,summary and optimize it,and then deduce an algorithm March C-SOF+ with high fault detection rate.(4)In the end,the hardware circuit description of the system is performed with Verilog HDL and introduce choose signal circuit and logical gating clock circuit for reducing the consumption of the chip,and then the configuration and simulation are performed with ISE and ISE ChipScope.