The Design And FPGA Implement Of A High-Performance Vector Coprocessor Arithmetic Unit

In order to meet the need of multimedia vector operations,the modern mainstream processor have expanded single instruction multimedia data(SIMD)instruction set so that the processor can execute the fast vector operations.PowerPC processor architecture as a RISC processor,jointly developed by the IBM corporation,Motorola Inc.,and Apple Computer Inc.also provides a vector operation instruction set,Altivec,expect their host processor instruction set.This instruction set provides high-speed vector operation ability for complex networking,multimedia,video,audio,and graphics applications.This thesis design the arithmetic units of a high-performance vector coprocessor for the Altivec instruction set,and by the PowePC processor reserved Auxiliary Processor Unit(APU)interface,combine this coprocessor with PowerPC host processor.This thesis also provides a top-level design of Altivec coprocessor architecture,the design of vector floating-point unit,vector complex fixed-point function unit and load/store unit,the combination design with PowerPC host processor.This thesis designed a modified floating-point computation algorithm of division,reciprocal,square root and inverse square root,based on look-up table and multiply method,and implement it to floating-point arithmetic unit.Finally,the design implemented on FPGA.In area aspect,the Altivec coprocessor in the Synopsis of.13 um tech,the total area is 2324669um2,and on the Xilinx Vertex6 xc6vcx75 t FPGA,LUT number is 131.The PowrPC405 with Altivec coprocessor in the Synopsis of.13 um tech,the total area is 3223547um2,and on the Xilinx Vertex6 xc6vcx75 t FPGA,LUT number is 33496.In speed aspect the Altivec coprocessor in the Synopsis of.13 um tech,the speed is 197 MHz,and on the Xilinx Vertex6 xc6vcx75 t FPGA,the speed is 153 MHz.The PowerPC with Altivec coprocessor in the Synopsis of.13 um tech,the speed is 127 MHz,and on the Xilinx Vertex6 xc6vcx75 t FPGA,the speed is 102 MHz.