The Double Errors Correction Algorithm Based On RRNS

With the rapid development of information technology today, People on the very-large-scale integrated circuit technology requirements are getting higher and higher. The integrated circuit process size has been close to the limit at present and Moore’s Law is about to fail. As a result, people to improve the circuit or system performance is no longer just by reducing the size of the process to achieve, but hope that through the algorithm to improve the front-end optimization and other ways to solve the system speed, area and low power problems.In the increasingly complex systems, such as communication systems, image processing systems, cryptosystems, radar systems, data processing systems, and so on are faced with VLSI performance problems, so parallel processing technolog y to become the object of various fields. The Residue Number System (RNS) is a typical parallel numerical representation system, which has the advantages of n atural parallelism, no power and fault tolerance, so it is one of the key research objects. In the past 20 years, the remainder of the system in the digital signal p rocessing and communications research more and more domestic and foreign rese arch results are also quite. At present, the research on the remainder system mai nly focuses on the fault-tolerant direction, and improves the reliability of the syst em by error detection and error correction by coding and decoding algorithm.Based on the above, this paper focuses on the error correction direction of t he remainder system, At present, the existing error correction algorithm has the f ollowing problems: 1. Most of the error correction algorithms are in a single err or correction, and no two or more than two in-depth study of error correction; 2.The existing double error or multiple error correction algorithm complexity is to o high and VLSI performance is poor, such as delay, the area is too large; Base d on the above two problems, this paper studies the algorithm based on RRNS double error correction, which obviously reduces the complexity of the algorithm and improves the VLSI performance.In this paper, a new error correction algorithm based on Redundant Residue System (RRNS) is proposed. The algorithm is based on the coding and decoding design method of linear block codes in traditional channel coding. Suitable for RRNS code codec design error correction algorithm, the main contents are as follows:1. Extended a two-error error correction algorithm theory and proposed improved error correction algorithm theory, The theory of double error correction algorithm is based on the correction corrector to correct the error. Firstly, the mapping table is established according to the corrector and the error. Then, the approximationcorrector is introduced by reducing the modulus and the multi-channel correction is added to the correction Mapping table to map the wrong output; The improved error correction algorithm theory is based on the approximate correction of theerror correction, through the value of all the possible value of the approximation of the correctness of the operator and the wrong mapping relationship, so as to achieve only a mapping table to complete error correction.In this paper, two algorithms are proposed: redundant correction matching algorithm and redundant traversal mapping algorithm, and the theoretical explanation is given.2. Based on the theory of corrective correction error correction algorithm and the algorithm of error correction based on approximate correction, two architectures based on RRNS decoding error correction algorithm are established. Both architectures include the three major modules: approximate base expansion and approximate correction sub-calculation module, error detection module and error correction module. In both architectures, all remainders are fed into independent parallel operations and do not interfere with each other, and their values are obtained by approximation of base and near correction. The two architectures differ only in the error detection module. The first architecture is based on the correction corrector for error detection. The second architecture is based on the approximate correction. Error correction modules are through the OR and MUX gate to step by step error correction options, this error mapping based on the structure of both thesystem to enhance the speed and save the hardware resources.Considering the compatibility problem, this paper also analyzes and discusses the error of the algorithm.3. This paper validates the Verilog HDL code and writes the VCS test platformto verify the algorithm, and realizes the complete verification and further buildsthe FPGA-based test platform to verify the algorithm. Finally, using the DesignCompiler tool and use the SMIC90 technology library to complete the code design synthesis and gate simulation and formal verification. This paper also makes a mistake to verify, by generating a single error mapping table and then build the corresponding test platform to verify that this algorithm can be compatible with a single error correction. This table mapping table generated by matlab programming and then import Verilog.4. In this paper, two typical two errors or multiple error correction algorithms based on RRNS are introduced in this paper. The error correction algorithm based on consistency equation detection and the iterative improvement based on Chinese Reminder Theory (CRT) Error algorithm. The code design, verification and synthesis of these two algorithms are used to compare the performance of the algorithm. In this paper, the algorithm of effective dynamic range width W = ∑i=1k[log2mi] 30bit will be evaluated from the aspects of delay, area and other performance, In this paper, the algorithm is reduced by 70.9% and 74.3%, respectively, while the area is increased by 44.9% and 184% respectively. The approximate algorithm is 74.7% and 77.7% A decrease of 30.9% compared with the other increased by 35.3%; In this paper, the algorithm is more suitable for VLSI implementation than the comparison algorithm,which is less than 57.8% and 27.1% respectively. The algorithm is less than 82.5% and 69.9% respectively. In order to evaluate the performance trend of each algorithm in different effective dynamic range, we also do 8bit and 16bit contrast analysis. In this case,the modified algorithm is 61.5% and 93.5% respectively compared with the two algorithms. Respectively, decreased by 84.1% and 97.3% respectively; For the 16bit, the proposed algorithm is less than 65.0% and 62.0%, respectively, and the algorithm is less than 82.2% and 80.6% respectively. Therefore, this algorithm is superior to the other two algorithms VLSI performance.